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參數(shù)資料
| 型號(hào)： | M32000D4 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE CHIP 32 BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片32位CMOS微機(jī) |
| 文件頁數(shù)： | 19/45頁 |
| 文件大小： | 535K |
| 代理商： | M32000D4 |
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SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
19
Bus interface unit (BIU)
The M32000D4AFP has the following signals related to the external
bus.
Address (A8 to A30)
The M32000D4AFP has a 24-bit address bus (A8 to A31) correspond-
ing to a 16 MB address space. Of these, A31 (the LSB) is not output
externally. In write cycles, the validity of the two bytes output on the
16-bit data bus is indicated by BCH and/or BCL. In read cycles, the
16-bit data bus is always read, however, only data in the valid byte
position in the M32000D4AFP is transferred. The address pins are
bidirectional. If the M32000D4AFP is in the hold state and the inter-
nal DRAM is accessed from an external bus master, the address
signal is input from the system bus side.
Space identifier (SID)
The space identifier is used to specify user space and I/O space.
user space: SID = "L"
I/O space: SID = "H"
hold: SID = high-impedance
idle: SID = undefined
Byte control (BCH, BCL)
Byte control signals indicate the byte position of valid data trans-
ferred of the external bus cycle. BCH corresponds to the MSB side
(D0 to D7), and BCL corresponds to the LSB side (D8 to D15). Dur-
ing the bus read cycle, both BCH and BCL are an "L" level. During
the bus write cycle, BCH and/or BCL go to an "L" level depending on
the bytes to be written. If the M32000D4AFP is in the hold state and
the internal DRAM is accessed from an external bus master, the byte
control signal is input from the system bus side.
Data bus (D0 to D15)
The M32000D4AFP has a 16-bit data bus to access external de-
vices. If the M32000D4AFP is in the hold state and the internal DRAM
is accessed from an external bus master, the data bus is used as a
data I/O bus from the system bus side.
Bus start (BS)
When the M32000D4AFP drives the bus cycle to the system bus, an
"L" level is output to BS at the start of the bus cycle. Also, for a burst
transfer, the BS signal is output for each transfer cycle. The BS sig-
nal is not output when accessing internal resources such as the in-
ternal DRAM or internal I/O registers.
Bus status (ST)
The ST signal identifies whether the bus cycle the M32000D4AFP is
driving is an instruction fetch cycle or an operand access cycle.
instruction fetch access: ST = "L"
operand access: ST = "H"
hold: ST = high-impedance
idle: ST = undefined
Read/write (R/W)
The M32000D4AFP outputs a R/W signal to identify whether the ex-
ternal bus cycle is a read or write operation. When accessing the
internal DRAM from an external bus master, a R/W signal is input
from the system bus side.
read bus cycle: R/W = "H"
Burst (BURST)
The M32000D4AFP drives two consecutive bus cycles to access 32-
bit data located on the 32-bit boundary. In instruction fetching, it drives
a maximum of 8 (fixed to 8 cycles in instruction cache mode) con-
secutive read cycles to access data located on the 128-bit boundary.
While driving these consecutive bus cycles, the M32000D4AFP out-
puts "L" level to BURST. When accessing 32-bit data, the address of
the MSB-side 16 bits are output before the address of the LSB side
16 bits. When accessing 128-bit data, the addresses are output for
every access cycle from the arbitrary 16-bit aligned addresses to
wraparound within the 128-bit boundary.
Data complete (DC)
When starting an external bus cycle, the M32000D4AFP automati-
cally inserts wait cycles until the DC signal is input from external.
Wait control using the DC signal is effective also for bus cycles dur-
ing burst transfer. When the M32000D4AFP is in the hold state and if
the CS signal is input, the M32000D4AFP outputs the DC signal to
notify the external bus master that internal DRAM access is com-
plete.
_____ _____
Hold control (HREQ, HACK)
The hold state is the state when the external bus access stops and
all pins go to a high-impedance state. However, the internal DRAM
can be accessed while the external bus is in the hold state. To put
the M32000D4AFP into the hold state, input an "L" level to HREQ.
When the hold request is accepted and the M32000D4AFP enters
the hold state, an "L" level is output from HACK.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M32000D4AFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE CHIP 32 BIT CMOS MICROCOMPUTER |
| M32000D4BFP-80 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER |
| M32002AGLJ | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:9x14 mm, 3.3/2.5/1.8 Volt, PECL/LVDS/CML, VCXO |
| M32002AGMJ | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:9x14 mm, 3.3/2.5/1.8 Volt, PECL/LVDS/CML, VCXO |
| M32002AGPJ | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:9x14 mm, 3.3/2.5/1.8 Volt, PECL/LVDS/CML, VCXO |
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