參數(shù)資料
型號(hào)： M32000D4
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE CHIP 32 BIT CMOS MICROCOMPUTER
中文描述： 單芯片32位CMOS微機(jī)
文件頁(yè)數(shù)： 24/45頁(yè)
文件大?。?/td> 535K
代理商： M32000D4
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
24
("L" output)
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
8
HREQ
BCH, BCL
D0 - D15
DC
R/W
hold shift
hold
return
HACK
A8 - A30
CS
read
read
read
read
Note:
"Hi-z" means high impedance, and indicates sampling timing.
cannot be changed during CS="L". Hold this value while CS="L".
8
, 3 to 7 CLKIN clock periods are necessary for
Also, where marked above with
signals during these wait cycle periods (DC = "H"). Consecutive read operations
within an 128-bit boundary are completed in 1 CLKIN clock period.
During these wait cycle period, CS cannot be returned to an "H" level (the access
cannot be aborted). CS can only be returned to an "H" level after DC is driven to "L".
CLKIN
The value of the R/W signal that controls the data direction of the bus interface
When the M32000D4AFP is in the hold state and an "L" level is input
to CS, the M32000D4AFP interprets it as a bus access request to
the internal DRAM. In this case, when the R/W signal is an "H" level,
the memory controller drives a read cycle to the internal DRAM. In
the read cycle, the 16-bit data for the address specified with A8 to
A30, is output from D0 to D15 regardless of the BCH and BCL set-
tings. Also the DC signal is output.
The M32000D4AFP reads 128 bits of data from the block on the
128-bit boundary including the requested address into the 128-bit
buffer of the bus interface unit. 3 to 7 CLKIN clock periods are neces-
sary for the first bus access, however, when reading consecutive
address within the 128-bit boundary, the subsequent read bus cycles
are completed in 1 CLKIN clock period because a read from the in-
ternal DRAM does not take place.
Once the external bus master read cycle has been driven, it cannot
be aborted. When an "L" level is input to CS and an access has
started, the values of this and other control signals should be held
during the wait cycles (that is while DC = "H"). After DC outputs an
"L" level (access complete), return CS to the "H" level between the
CLKIN falling edge corresponding to the last read cycle and the fol-
lowing CLKIN falling edge. Return HREQ to the "H" level to return
the M32000D4AFP to the normal operation mode from the hold state
either at the same time as or after CS is returned to the "H" level.
Fig. 23 Read bus cycle to internal DRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M32000D4AFP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE CHIP 32 BIT CMOS MICROCOMPUTER
M32000D4BFP-80 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
M32002AGLJ 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:9x14 mm, 3.3/2.5/1.8 Volt, PECL/LVDS/CML, VCXO
M32002AGMJ 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:9x14 mm, 3.3/2.5/1.8 Volt, PECL/LVDS/CML, VCXO
M32002AGPJ 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:9x14 mm, 3.3/2.5/1.8 Volt, PECL/LVDS/CML, VCXO
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