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參數(shù)資料
| 型號： | M34570EDFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDSO36 |
| 封裝： | 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-36 |
| 文件頁數(shù)： | 44/69頁 |
| 文件大?。?/td> | 687K |
| 代理商： | M34570EDFP |
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Under
development
Preliminary Specifications REV.1.02
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
49
Processor Mode
Figure 1.6.1. PM0 Register
0 0 : Multiplex bus is not used
0 1 : Allocated to CS2 space
0 1 : Allocated to CS1 space
1 1 : Allocated to entire CS space6
Notes :
1. The PM0 registers should be set after the PRC1 bit in the PRCR register is set to "1".
2. Processor mode is not exited even if setting the PM03 bit to "1" .
3. Avoid setting the PM01 to PM00 bits and other bits simultaneously when setting the PM01 to PM00 bits
to "012" or "112". Another bits should be set first to rewrite before setting the PM01 to PM00 bits.
4. When using 16-bit data bus in DRAMC controler, this bit should be set to "1".
5. This bit is available in microprocessor and memory expansion modes.
The PM05 to PM04 bits should be set to "002" in mode 0.
Avoid setting the PM05 to PM04 bits to "012" in mode 2.
6. The PM05 to PM04 bits cannot be set to "112" in microprocessor mode since a separate bus is
performed after reset.
When setting the PM05 to PM04 bits to "112" in memory expansion mode, space to be accessed is
64K bytes per chip-select. CS0 to CS2 are selected in mode 1, CS0 and CS1 in mode 2 and CS0 to
CS3 in mode 3.
7. No BCLK is output in single-chip mode even if the PM07 bit is set to "0". When halting a clock output
in microprocessor or memory expansion mode, the PM07 bit should be set to "1" and the CM01 to
CM00 bits in the CM0 register be set to "002" (I/O port P53). "L" is output from P53.
8. When setting the PM07 bit to "0" (BCLK output), the CM01 and CM00 bits should be set to "002".
Symbol
Address
When reset
PM0
000416
1000 00002 (CNVss = "L")
0000 00112 (CNVss = "H")
Processor mode register 01
RW
b1 b0
b5 b4
0: RD / BHE / WR
1: RD / WRH / WRL
PM00
PM01
PM02
PM03
Software reset bit
R/W mode select bit4
PM04
PM05
0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Avoid this setting
1 1: Microprocessor mode
Should set to "0"
PM07
BCLK output disable bit7
Reserved bit
0 : BCLK is output8
1 : BCLK is not output
The CM01 and CM00 bits in the
CM0 register determine functions.
The microcomputer is reset when
this bit is set to "1". When read, its
content is indeterminate.
Bit name
Function
Bit
symbol
Processor mode bit2, 3
Multiplex bus space
select bit5
b7
b6
b5
b4
b3
b2
b1
b0
0
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