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參數(shù)資料
| 型號： | M34570EDFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDSO36 |
| 封裝： | 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-36 |
| 文件頁數(shù)： | 48/69頁 |
| 文件大?。?/td> | 687K |
| 代理商： | M34570EDFP |
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Under
development
Preliminary Specifications REV.1.02
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
53
Bus
(1) Selecting External Address Bus
The number of address bus for external output, the number of chip-selects and chip-select space vary
depending on each external space mode. The PM11 to PM10 bits in the PM1 register determine an
external space mode.
With DRAMC, row addresses and column addresses are multiplexed to output in a DRAM space.
(2) Selecting External Data Bus
8 bits or 16 bits can be selected for external data bus in the DS register per external space. Data bus in
the external space 3, after reset, becomes 16 bits wide when an input to the BYTE pin is set to "L" and 8
bits wide when it is set to "H". Avoid changing the BYTE pin input level during operation. Internal bus is
always 16 bits wide.
(3) Selecting Separate/Multiplex Bus
The PM05 to PM04 bits in the PM0 register determine either a separate or multiplex bus as bus format .
Separate Bus
Data and address are separated for input and output. The DS register determines an external data
bus width, 8-bit data bus or 16-bit, per external space. When all DSi bits in the DS register (i=0 to 3)
are set to "0" (8-bit data bus), port P0 becomes a data bus and port P1 becomes a programmable I/O
port. When setting one of the DSi bits to "1" (16-bit data bus), ports P0 and P1 become the data bus.
When setting the DSi bits to "0", port P1 is indeterminate.
With a separate bus, the WCR register determines a software wait status.
Multiplex Bus
Data and address are timeshared for input and output. D0 to D7 are multiplexed with A0 to A7 in 8-bit
space selected by the DSi bit. D0 to D15 are multiplexed with A0 to A15 in16-bit space selected by the
DSi bit. In the multiplex bus space, the WCR register selects two waits or three waits. Two-wait access
is automatically selected even if either no wait, one wait or two waits is selected. Refer to the para-
graph "(4) Bus Timing" for details.
In memory expansion mode, when the PM05 to PM04 bits in the PM register are set to "112" (allocated
____
to entire CS space), only 16 bits from A0 to A15 are output as an address.
The PM05 to PM04 bits cannot set to "112" in microprocessor mode. See Table 1.7.2 for details.
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