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參數資料
| 型號： | M34570EDFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDSO36 |
| 封裝： | 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-36 |
| 文件頁數： | 52/69頁 |
| 文件大小： | 687K |
| 代理商： | M34570EDFP |
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Under
development
Preliminary Specifications REV.1.02
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
57
Bus
(3) Read and Write Signals
With a 16-bit data bus, the PM02 bit in the PM0 register determines the read and write signals, a combi-
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nation of the RD, WR and BHE signals or the RD, WRL and WRH signals. When the DS3 to DS0 bits in
the DS register is set to "0" (all 8-bit data bus in external memory space), the PM02 bit should be set to "0"
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(RD, WR and BHE). When setting some of the DS3 to DS0 bits to "1" (16-bit data bus) to access an 8-bit
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space, a combination of RD, WR and BHE is automatically selected regardless of the PM02 bit. Tables
1.7.3 and 1.7.4 list each signal operations.
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RD, WR and BHE are combined for read and write signals after reset.
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When changing a combination of RD, WRL and WRH, the PM02 bit should be set first to write to an
external memory.
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When accessing the DRAM with a 16-bit bus, the PM02 bit should be set to "1" (RD, WRL and WRH).
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Table 1.7.3. RD, WRL and WRH Signals
Status of external data bus
RD
BHE
WR
HL
L
LHL
HLH
LH
H
Write 1-byte data to odd address
Read 1-byte data from odd address
Write 1-byte data to even address
Read 1-byte data from even address
Data bus
A0
H
L
HL
L
LHL
L
HL
H / L
LH
H / L
8 bits
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1-byte data
Read 1-byte data
16 bits
Not used
Status of external data bus
Read data
Write 1-byte data to even address
Write 1-byte data to odd address
Write data to both even and odd addresses
WRH
WRL
RD
Data bus
16 bits
H
L
H
L
H
L
H
H 1
L 1
L
Not used
Write 1-byte data
Read 1-byte data
Not used
8 bits
Notes :
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1. The WR signal is set.
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Table 1.7.4. RD, WR and BHE Signals
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