參數(shù)資料
型號(hào): M34570EDFP
元件分類(lèi): 微控制器/微處理器
英文描述: 4-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDSO36
封裝: 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-36
文件頁(yè)數(shù): 51/69頁(yè)
文件大?。?/td> 687K
代理商: M34570EDFP
Under
development
Preliminary Specifications REV.1.02
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
56
Bus
Figure 1.7.2. Address Bus and Chip-Select Signal Outputs (Separate bus)
Example 1:
When accessing external space j specified by another
chip-select signal in the next cycle after having
accessed external space i, both address bus and
chip-select signal change.
Notes :
1. The above applies to address bus and chip-select signal in two consecutive cycles.
By combining these examples, chip-select signal may output two or more cycles.
Data bus
Address bus
Chip select
CSk
Access
external
space i
Chip select
CSp
Access
external
space j
Address
Data
Example 2:
When accessing internal ROM/RAM space in the
next cycle after having accessed external space,
the chip-select signal changes but the address bus
does not.
Example 3:
When accessing the space i specified by the same
chip-select signal in the next cycle after having
accessed external space i, address bus changes but
the chip-select signal does not.
Data bus
Address bus
Chip select
CSk
Data
Address
Data bus
Address bus
Chip select
CSk
Data
Address
Access to
external
space
No access
Access to
external
space i
Access to
external
space i
Data bus
Address bus
Chip select
CSk
Data
Address
Example 4:
When CPU does not access any space in the next
cycle after having accessed external space (no pre-
fetch of an instruction is generated), niether address
bus nor the chip select signal change .
Data
Access
external
space
Access
internal
ROM/RAM
space
i = 0 to 3
k = 0 to 3
j = 0 to 3, excluding i
p= 0 to 3, excluding k
(See Figure 1.6.3 about i, j and p, k)
k = 0 to 3
i = 0 to 3
k = 0 to 3
(See Figure 1.6.3 about i and k)
k = 0 to 3
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