- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄69011 > M34570EDFP 4-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDSO36 PDF資料下載
參數(shù)資料
| 型號： | M34570EDFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDSO36 |
| 封裝： | 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-36 |
| 文件頁數(shù)： | 60/69頁 |
| 文件大?。?/td> | 687K |
| 代理商： | M34570EDFP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁當前第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁
Under
development
Preliminary Specifications REV.1.02
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
64
Bus
Table 1.7.7. Microcomputer Status in a Hold State
Item
Status
Oscillation
On
_____
________
_________
_____
_______
RD, WR, WRL, WRH, address bus, data bus, CS, BHE
High-impedance
Programmable I/O ports: P0 to P15
__________
Maintains status when HOLD signal is received
__________
HLDA
Output "L"
Internal peripheral circuits
On (except the watchdog timer stops)
ALE signal
Output "L"
(8) External Bus Status when Accessing Internal Space
Table 1.7.8 shows external bus status when accessing internal space.
Table 1.7.8. External Bus State when Accessing Internal Space
Item
State when accessing SFR, internal ROM and internal RAM
Address bus
Maintains address of external space accessed immediately before
Data bus
When read
High-impedance
When write
High-impedance
_____
______
________
_________
RD, WR, WRL, WRH
Output "H"
________
BHE
Maintains in an external space state accessed immediately before
____
CS
Output "H"
ALE
Output ALE
(9) BCLK Output
The CPU clock is a clock to operate the CPU. When combining the PM07 bit in the PM0 register set to "0"
(BCLK output) and the CM01 to CM00 bits in the CM0 register set to "002", the CPU clock signal is output
from P53 as BCLK.
No BCLK is output in single-chip mode. Refer to the section "System Clock" for details.
_______
__________
_____
(10) DRAM Control Signals (RAS, CASL, CASH and DW)
The DRAM control signals control DRAM. The DRAM control signals are output when the AR0 to AR2
bits in the DRAMCONT register determines a DRAM space. Table 1.7.9 lists each signal operation.
_______
__________
_____
Table 1.7.9. RAS, CASL, CASH and DW Signals
Status of external data bus
RAS
CASH
CASL
LLL
LL
H
LL
H
LLL
Read data from both even and odd addresses
Read 1-byte data from even address
Read 1-byte data from odd address
Write data to both even and odd addresses
Data bus width
DW
H
L
LL
H
L
LHL
L
LL
H
LL
L
8 bits
Write 1-byte data to even address
Write 1-byte data to odd address
Read 1-byte data
Write 1-byte data
16 bits
Not used
相關PDF資料 |
PDF描述 |
|---|---|
| M34570M4-XXXFP | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, PDSO36 |
| M34570M8-XXXFP | 4-BIT, MROM, MICROCONTROLLER, PDSO36 |
| M34570EDFP | 4-BIT, OTPROM, MICROCONTROLLER, PDSO36 |
| M34584EDFP | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO42 |
| M34584MD-XXXFP | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO42 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M34570M4 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34570M4-081FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34570M4-202FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34570M4-214FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34570M4-227FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
發(fā)布緊急采購，3分鐘左右您將得到回復。