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參數(shù)資料
| 型號(hào)： | M36DR432BD |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256Kb x16 SRAM, Multiple Memory Product |
| 中文描述： | 32兆位的2Mb x16插槽，雙行，頁閃存和4兆位的256Kb x16的SRAM，多個(gè)存儲(chǔ)產(chǎn)品 |
| 文件頁數(shù)： | 42/52頁 |
| 文件大小： | 834K |
| 代理商： | M36DR432BD |
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M36DR432AD, M36DR432BD
42/52
Table 24. SRAM Write AC Characteristics
Note: 1. t
AS
is measured from the address valid to the beginning of write.
2. t
WR
is measured from the end or write to the address change. t
WR
applied in case a write ends as ES or WS goes High.
3. t
CW
is measured from ES going Low end of write.
4. A Write occurs during the overlap (t
WP
) of Low ES and Low WS. A write begins when ES goes Low and WS goes Low with asserting
UBS or LBS for single byte operation or simultaneously asserting UBS and LBS for double byte operation. A write ends at the ear-
liest transition when ES goes High and WS goes High. The t
WP
is measured from the beginning of write to the end of write.
Figure 24. SRAM Low V
DDS
Data Retention AC Waveforms, ES Controlled
Symbol
Alt
Parameter
SRAM
Unit
70
Min
Max
t
AVAV
t
WC
Write Cycle Time
70
ns
t
AVEL
t
AS (1)
Address Valid to Chip Enable Low
0
ns
t
AVWH
t
AW
Address Valid to Write Enable High
60
ns
t
AVWL
t
AS (1)
Address Valid to Write Enable Low
0
ns
t
BLWH
t
BW
UBS, LBS Valid to End of Write
60
ns
t
DVWH
t
DW
Input Valid to Write Enable High
30
ns
t
EHAX
t
WR (2)
Chip Enable High to Address Transition
0
ns
t
ELWH
,
t
CW
(3)
Chip Select to End of Write
60
ns
t
WHAX
t
WR (2)
Write Enable High to Address Transition
0
ns
t
WHDX
t
DH
Write Enable High to Input Transition
0
ns
t
WHQX
t
OW
Write Enable High to Output Transition
10
ns
t
WLQZ
t
WHZ
Write Enable Low to Output Hi-Z
25
ns
t
WLWH
t
WP (4)
Write Enable Pulse Width
50
ns
AI07325
1.65 V
VDR
≥
ES
tCDR
ES
≥
VDDS – 0.2V
1.0 V
VDDS
tR
DATA RETENTION MODE
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