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參數(shù)資料
| 型號： | M39432 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Single Chip 4Mbit Flash and 256Kbit Parallel EEPROM Memory(單片4Mb閃速和256Kb并行EEPROM) |
| 中文描述： | 單芯片的4Mb并行閃存和256Kbit EEPROM存儲器（單片4Mb的閃速和256Kb的并行的EEPROM） |
| 文件頁數(shù)： | 3/30頁 |
| 文件大?。?/td> | 247K |
| 代理商： | M39432 |
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64K Bytes Block
AI01362B
7FFFFh
6FFFFh
5FFFFh
4FFFFh
3FFFFh
2FFFFh
1FFFFh
0FFFFh
TOP
ADDRESS
70000h
60000h
50000h
40000h
30000h
20000h
10000h
00000h
BOTTOM
ADDRESS
A18
1
1
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64K Bytes Block
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A17
1
1
A16
1
0
1
1
0
0
1
0
0
0
1
1
1
0
0
0
1
0
0
0
Figure 3. Flash Memory Map and Block Address Table
Data Input/Output (DQ0-DQ7).
A write operation
inputs one byte which is latched when
EE (or EF)
and Write Enable W are driven active.
Data read is valid when one Chip Enable (Chip
Enable Flash or Chip Enable EEPROM) and Out-
put Enable are driven active. The output is high
impedance when the chip is deselected (both EE
and EF driven high) or the outputs are disabled (G
driven high).
Read operations are used to output the contents
from the memory, the Manufacturer identifier, the
Flash Sector protection Status, the Flash block
Identifier, the EEPROM identifier or the OTP row
content.
Memory Block Enable (EE and EF).
The Memory
Block Enable (EE or EF) activates the memory
control logic, input buffers, decoders and sense
amplifiers. When the EE input is driven high, the
EEPROM memory block is not selected; when the
EF input is driven high, the Flash memory block is
not selected. Attempts to access both EEPROM
and Flash blocks (EE low and EF low) are forbid-
den. Switching between the two memory block
enables (EE and EF) must not be made on the
same clock cycle, a delay of greater than t
EHFL
must
be inserted.
The M39432 is in standby when both EF and EE
are High (when no internal Erase or programming
is running). The power consumption is reduced to
the standby level and the outputs are in the high
impedance state, independent of the Output En-
able G or Write Enable W inputs.
After 150ns of inactivity and when the addresses
are driven at CMOS levels, the chip automatically
enters a pseudo standby mode where consumption
is reduced to the CMOS standby value, while the
outputs continue to drive the bus.
Output Enable (G).
The Output Enable gates the
outputs through the data buffers during a read
operation. The data outputs are in the high imped-
ance state when the Output Enable G is High.
During Sector Protect and Sector Unprotect opera-
tions, the G input must be forced to V
ID
level (12V
+ 0.5V) (for Flash memory block only).
Write Enable (W).
Addresses are latched on the
falling edge of W, and Data Inputs are latched on
the rising edge of W.
Ready/Busy (R/B).
The Ready/Busy pin outputs
the status of the device when the EEPROM mem-
ory block is under the write condition
– R/B = ’0’: internal writing is in process,
– R/B = ’1’: no internal writing in in process.
It should be noted that the Ready/Busy pin does
not reflect the status of Programming/Erasing in the
Flash memory.
This status bit can be used when reading (or fetch-
ing opcodes) in the Flash memory block.
The Ready/Busy output uses an open drain tran-
sistor, allowing therefore the use of the M39432 in
multi-memory applications with all Ready/Busy out-
puts connected to a single Ready/Busy line (OR-
wired with an external pull-up resistor).
3/30
M39432
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| M39432-10VNC6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Single Chip 4 Mbit Flash Memory and 256 Kbit Parallel EEPROM |
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| M39432-12VNC6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Single Chip 4 Mbit Flash Memory and 256 Kbit Parallel EEPROM |
| M39432-12WNC6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Single Chip 4 Mbit Flash Memory and 256 Kbit Parallel EEPROM |
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