249
Atmel ATmega16/32/64/M1/C1 [DATASHEET]
7647K–AVR–12/13
24.7.10 Reading the Signature Row from Software
To read the signature row from software, load the Z-pointer with the signature byte address given in
Table 24-5 on page 249 and
set the SIGRD and SPMEN bits in SPMCSR. When an LPM instruction is executed within three CPU cycles after the SIGRD
and SPMEN bits are set in SPMCSR, the signature byte value will be loaded in the destination register. The SIGRD and
SPMEN bits will auto-clear upon completion of reading the signature row lock bits or if no LPM instruction is executed within
three CPU cycles. When SIGRD and SPMEN are cleared, LPM will work as described in the instruction set manual.
Note:
Before attempting to set SPMEN it is important to test this bit is cleared showing that the hardware is ready for a
new operation.
Note:
All other addresses are reserved for future use.
24.7.11 Preventing Flash Corruption
During periods of low VCC, the flash program can be corrupted because the supply voltage is too low for the CPU and the flash
to operate properly. These issues are the same as for board level systems using the flash, and the same design solutions
should be applied.
A flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the
flash requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply
voltage for executing instructions is too low.
Flash corruption can easily be avoided by following these design recommendations (one is sufficient):
1.
If there is no need for a boot loader update in the system, program the boot loader lock bits to prevent any boot loader
software updates.
2.
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling
the internal brown-out detector (BOD) if the operating voltage matches the detection level. If not, an external low VCC
reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be
completed provided that the power supply voltage is sufficient.
3.
Keep the AVR core in power-down sleep mode during periods of low VCC. This will prevent the CPU from attempting
to decode and execute instructions, effectively protecting the SPMCSR register and thus the flash from unintentional
writes.
24.7.12 Programming Time for Flash when Using SPM
The calibrated RC oscillator is used to time flash accesses.
Table 24-6 shows the typical programming time for flash accesses
from the CPU.
Table 24-5. Signature Row Addressing
Signature Byte
Z-Pointer Address
Device signature byte 1
0x0000
Device signature byte 2
0x0002
Device signature byte 3
0x0004
RC oscillator calibration byte
0x0001
TSOFFSET temp sensor offset
0x0005
TSGAIN temp sensor gain
0x0007
Table 24-6. SPM Programming Time
Symbol
Min Programming Time
Max Programming Time
Flash write (page erase, page write, and write lock
bits by SPM)
3.7ms
4.5ms