
297
Atmel ATmega16/32/64/M1/C1 [DATASHEET]
7647K–AVR–12/13
BRBS
s, k
Branch if status flag Set
if (SREG(s) = 1) then PC
← PC+k + 1
None
1/2
BRBC
s, k
Branch if status flag cleared
if (SREG(s) = 0) then PC
← PC+k + 1
None
1/2
BREQ
k
Branch if equal
if (Z = 1) then PC
← PC + k + 1
None
1/2
BRNE
k
Branch if not equal
if (Z = 0) then PC
← PC + k + 1
None
1/2
BRCS
k
Branch if carry set
if (C = 1) then PC
← PC + k + 1
None
1/2
BRCC
k
Branch if carry cleared
if (C = 0) then PC
← PC + k + 1
None
1/2
BRSH
k
Branch if same or higher
if (C = 0) then PC
← PC + k + 1
None
1/2
BRLO
k
Branch if lower
if (C = 1) then PC
← PC + k + 1
None
1/2
BRMI
k
Branch if minus
if (N = 1) then PC
← PC + k + 1
None
1/2
BRPL
k
Branch if plus
if (N = 0) then PC
← PC + k + 1
None
1/2
BRGE
k
Branch if greater or equal, signed
if (N
⊕ V= 0) then PC ← PC + k + 1
None
1/2
BRLT
k
Branch if less than zero, signed
if (N
⊕ V= 1) then PC ← PC + k + 1
None
1/2
BRHS
k
Branch if half carry flag set
if (H = 1) then PC
← PC + k + 1
None
1/2
BRHC
k
Branch if half carry flag cleared
if (H = 0) then PC
← PC + k + 1
None
1/2
BRTS
k
Branch if T flag set
if (T = 1) then PC
← PC + k + 1
None
1/2
BRTC
k
Branch if T flag cleared
if (T = 0) then PC
← PC + k + 1
None
1/2
BRVS
k
Branch if overflow flag is set
if (V = 1) then PC
← PC + k + 1
None
1/2
BRVC
k
Branch if overflow flag is cleared
if (V = 0) then PC
← PC + k + 1
None
1/2
BRIE
k
Branch if interrupt enabled
if (I = 1) then PC
← PC + k + 1
None
1/2
BRID
k
Branch if interrupt disabled
if (I = 0) then PC
← PC + k + 1
None
1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
Set bit in I/O register
I/O(P,b)
← 1
None
2
CBI
P,b
Clear bit in I/O register
I/O(P,b)
← 0
None
2
LSL
Rd
Logical shift left
Rd(n+1)
← Rd(n), Rd(0) ← 0
Z,C,N,V
1
LSR
Rd
Logical shift right
Rd(n)
← Rd(n+1), Rd(7) ← 0
Z,C,N,V
1
ROL
Rd
Rotate left through carry
Rd(0)
← C,Rd(n+1)← Rd(n),C← Rd(7)
Z,C,N,V
1
ROR
Rd
Rotate right through carry
Rd(7)
← C,Rd(n)← Rd(n+1),C← Rd(0)
Z,C,N,V
1
ASR
Rd
Arithmetic shift right
Rd(n)
← Rd(n+1), n=0..6
Z,C,N,V
1
SWAP
Rd
Swap nibbles
Rd(3..0)
← Rd(7..4),Rd(7..4)← Rd(3..0)
None
1
BSET
s
Flag set
SREG(s)
← 1
SREG(s)
1
BCLR
s
Flag clear
SREG(s)
← 0
SREG(s)
1
BST
Rr, b
Bit store from register to T
T
← Rr(b)
T
1
BLD
Rd, b
Bit load from T to register
Rd(b)
← T
None
1
SEC
Set carry
C
← 1
C
1
CLC
Clear carry
C
← 0
C
1
SEN
Set negative flag
N
← 1
N
1
CLN
Clear negative flag
N
← 0
N
1
SEZ
Set zero flag
Z
← 1
Z
1
CLZ
Clear zero flag
Z
← 0
Z
1
SEI
Global interrupt enable
I
← 1
I
1
CLI
Global interrupt disable
I
← 0
I
1
SES
Set signed test flag
S
← 1
S
1
CLS
Clear signed test flag
S
← 0
S
1
SEV
Set twos complement overflow.
V
← 1
V
1
CLV
Clear twos complement overflow
V
← 0
V
1
SET
Set T in SREG
T
← 1
T
1
28.
Instruction Set Summary (Continued)
Mnemonics
Operands
Description
Operation
Flags
#Clocks
Note:
1.
These Instructions are only available in “16K and 32K parts”