參數(shù)資料
型號： M68HC705UGANG
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
中文描述： 高密度互補金屬氧化物半導(dǎo)體（HCMOS）微控制器
文件頁數(shù)： 50/112頁
文件大?。?/td> 809K
代理商： M68HC705UGANG
7-4
MC68HC05BD3
M-BUS SERIAL INTERFACE
7
7.2.3
Data Transfer
Once a successful slave addressing is achieved, the data transfer can proceed byte by byte in a
direction specified by the R/W bit sent by the calling master.
Each data byte is 8 bits long. Data can be changed only when SCL is low and must be held stable
when SCL is high as shown in Figure 7-2. One clock pulse is for one bit of data transfer, MSB is
transferred first. Each data byte has to be followed by an acknowledge bit. Hence, one complete
data byte transfer requires 9 clock pulses.
If the slave receiver does not acknowledge the master, the SDA line should be left high by the
slave, the master can then generate a STOP signal to abort the data transfer or a START signal
(repeated START) to commence a new calling.
If the master receiver does not acknowledge the slave transmitter after one byte transmission, it
means an “end of data” to the slave. The slave shall release the SDA line for the master to
generate STOP or START signal.
7.2.4
Repeated START Signal
As shown in Figure 7-2, a repeated START signal is to generate a START signal without first
generating a STOP signal to terminate the communication. This is used by the master to
communicate with another slave or with the same slave in a different mode (transmit/receive
mode) without releasing the bus.
7.2.5
STOP Signal
The master can terminate the communication by generating a STOP signal to free the bus.
However, the master may generate a START signal followed by a calling command without
generating a STOP signal first. This is called repeat START. A STOP signal is defined as a low to
high transition of SDA while SCL is at a logical high; see Figure 7-2.
7.2.6
Arbitration Procedure
This interface circuit is a true multi-master system which allows more than one master to be
connected. If two or more masters try to control the bus at the same time, a clock synchronization
procedure determines the bus clock. The clock low period is equal to the longest clock low period
among the masters; and the clock high period is the shortest among the masters. A data
arbitration procedure determines the priority. A master will lose arbitration if it transmits a logic “1”
while the others transmit logic “0”, the losing master will immediately switch over to slave receive
mode and stops its data and clock outputs. The transition from master to slave mode will not
generate a STOP condition. Meanwhile, a software bit will be set by hardware to indicate loss of
arbitration.
TPG
48
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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