參數(shù)資料
型號: M68HC705UGANG
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
中文描述: 高密度互補(bǔ)金屬氧化物半導(dǎo)體(HCMOS)微控制器
文件頁數(shù): 96/112頁
文件大小: 809K
代理商: M68HC705UGANG
12-4
MC68HC05BD3
ELECTRICAL SPECIFICATIONS
12
12.5
M-Bus Timing
Table 12-3
M-Bus Interface Input Signal Timing
(V
DD
=5.0Vdc
±
10%, V
SS
=0Vdc, temperature range=0 to 70
°
C)
PARAMETER
START condition hold time
Clock low period
Clock high period
Data set-up time
Data hold time
START condition set-up time
(for repeated START condition only)
STOP condition set-up time
SYMBOL
t
HD.STA
t
LOW
t
HIGH
t
SU.DAT
t
HD.DAT
MINIMUM
2
4.7
4
250
0
MAXIMUM
UNIT
t
CYC
t
CYC
t
CYC
ns
t
CYC
t
SU.STA
2
t
CYC
t
SU.STO
2
t
CYC
Table 12-4
M-Bus Interface Output Signal Timing
(V
DD
=5.0Vdc
±
10%, V
SS
=0Vdc, temperature range=0 to 70
°
C)
PARAMETER
START condition hold time
Clock low period
Clock high period
SDA/SCL rise time (see note 1)
SDA/SCL fall time (see note 1)
Data set-up time
Data hold time
START condition set-up time
(for repeated START condition only)
STOP condition set-up time
Note:
SYMBOL
t
HD.STA
t
LOW
t
HIGH
t
R
t
F
t
SU.DAT
t
HD.DAT
MINIMUM
8
11
11
t
LOW
– t
CYC
1
MAXIMUM
1
300
UNIT
t
CYC
t
CYC
t
CYC
μ
s
ns
ns
t
CYC
t
SU.STA
10
t
CYC
t
SU.STO
10
t
CYC
1. With 200pF loading on the SDA/SCL pins
Figure 12-1
M-Bus Timing
SDA
SCL
t
HIGH
t
HD.STA
t
LOW
t
SU.DAT
t
HD.DAT
t
SU.STA
t
SU.STO
t
R
t
F
TPG
94
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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