參數(shù)資料
型號: M7010R-066ZA1T
廠商: 意法半導體
英文描述: 16K x 68-bit Entry NETWORK SEARCH ENGINE
中文描述: 16K的× 68位進入網絡搜索引擎
文件頁數(shù): 18/67頁
文件大小: 449K
代理商: M7010R-066ZA1T
M7010R
18/67
CLOCKS
The M7010R receives a Clock (CLK2X) signal and
Phase (PHS_L) signal. The Phase (PHS_L) di-
vides the CLK2X signal to generate the Internal
Clock (CLK), as shown in Figure 12. The CLK2X
and CLK signals are used for internal operations.
Registers
All the M7010R registers are 68 bits wide. The
M7010R contains 32 comparand storage regis-
ters, 16 global mask registers, 8 SEARCH-suc-
cessful index registers, command, information,
burst READ, burst WRITE, and next free address
registers. Table 8 provides a register overview of
all the registers. The registers are ordered in as-
cending address order.
Comparand Registers
The device contains thirty-two 68-bit comparand
registers dynamically selected in every SEARCH
operation to store the comparand presented on
the DQ Bus. The LEARN command will also use
these registers when it is executed. The M7010R
stores the SEARCH command
s
Cycle A
com-
parand in the even-number register and the
Cycle
B
comparand in the odd-numbered register, as
shown in Figure 13, page 19.
Mask Registers
The device contains sixteen (8 pairs) 68-bit global
mask registers dynamically selected in every
SEARCH operation to select the SEARCH sub-
field (see Figure 14, page 19). The three-bit GMR
Index supplied on the CMD bus applies eight pairs
of global masks during the SEARCH and WRITE
operations, also shown in Figure 14.
Note:
In 68-bit SEARCH and WRITE operations,
the host ASIC must program the even and odd
mask register with the same values, and the
M7010R uses even-numbered mask registers as
global masks.
Each mask bit in the global mask registers is used
during
SEARCH
and WRITE operations. In
SEARCH operations, setting the Mask Bit to '1' en-
ables compares; setting the Mask Bit to '0' dis-
ables compares (forced match) at the current bit
position. In WRITE operations to the data or mask
array, setting the Mask Bit to '1' enables WRITEs;
setting the Mask Bit to '0' disables WRITEs at the
corresponding bit position.
Figure 12. Clocks
Note: Any reference to
CLK Cycles
means 2 cycles of the signal,
CLK2X.
1.
CLK
is an internal signal. The period for this clock is specified in Table 7, page 15.
Table 8. Register Overview
Address
Abbreviation
Type
Name
0
31
COMP0
31
R
32 Comparand Registers. Stores comparands from the DQ Bus for
learning later.
32
47
MASKS
RW
16 Global Mask Registers Array.
48
55
SSR0
7
R
8 SEARCH Successful Index Registers.
56
COMMAND
RW
Command Register.
57
INFO
R
Information Register.
58
RBURREG
RW
Burst READ Register.
59
WBURREG
RW
Burst WRITE Register.
60
NFA
R
Next Free Address Register.
61
63
Reserved
CLK2X
PHS_L
CLK(1)
AI04274
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