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參數(shù)資料
| 型號： | M7010R-066ZA1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 16K x 68-bit Entry NETWORK SEARCH ENGINE |
| 中文描述： | 16K的× 68位進(jìn)入網(wǎng)絡(luò)搜索引擎 |
| 文件頁數(shù)： | 19/67頁 |
| 文件大?。?/td> | 449K |
| 代理商： | M7010R-066ZA1T |
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M7010R
Figure 13. Comparand Register Selection
During SEARCH and LEARN
Figure 14. Addressing the Global Mask
Register (GMR) Array
SEARCH-Successful Registers
The device contains eight SEARCH-successful
registers (SSRs) to hold the index of the location
where a successful search occurred. The format of
each register is described in Table 9. The
SEARCH command specifies which SSR stores
the index of a specific SEARCH command in
“
Cy-
cle B
”
of the SEARCH Instruction.
After the index location is specified, the host ASIC
can use this register to access that data array,
mask array, or external SRAM using the index as
part of the address (see SRAM ADDRESSING,
page 58). The device with a valid bit set performs
a READ or WRITE operation. All other devices
suppress the operation.
Table 9. SEARCH-Successful Register (SSR) Description
135
0
68
68
1
3
5
7
0
2
4
6
30
31
0
1
15
Address
Index
AI04275
135
0
68
68
1
3
5
7
9
0
2
4
6
8
11
13
15
10
12
14
0
1
2
3
6
7
5
4
Address
Index
AI04276
SEARCH and WRITE Command
Global Mask Selection
Field
Range
Initial Value
Description
INDEX
[13:0]
X
Index.
This is the address of the 68-bit entry where a successful search
occurs. The device updates this field if it has a successful search. In 136-bit,
the LSB is '0;' in a 272-bit configuration, the two LSBs are '00.' The index
updates if the device is either a local or global winner in a SEARCH
operation.
–
[30:14]
0
Reserved.
VALID
[31]
0
Valid.
The device sets this bit to '1' if it is a global winner (first device
downstream with a hit) in a SEARCH operation, in a depth-cascaded
configuration.
–
[67:32]
0
Reserved.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M7010R-083ZA1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:16K x 68-bit Entry NETWORK SEARCH ENGINE |
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