M7010R
22/67
SEARCH PROCEDURE FOR 32-BIT WIDE PREFIXES
The Global Mask Register is used for 32-bit wide
data paths as follows:
Writing a '1' in the Global Mask Register allows
data to be written into the M7010R. A '0' in the Glo-
bal Mask Register disallows data modification. In-
formation is written into the left half of the 68-bit
word Search Engine as long as space for 34 bits
of data is available and then into the right half of
the Search Engine. 32-bit data can be entered in
two cycles.
The first step is to write into two of the eight Global
Mask Registers with the patterns shown in Figure
15. Writing this data using Global Mask Register 1
allows the left half of the data array to be com-
pletely filled.
Figure 16 shows Bits 67 through 36 in the left sec-
tion of the data array representing 32-bits of data.
Bits 35 and 34 shown separately can be defined
by the user for table management. In this applica-
tion 34-bit operation occurs in each half-section of
the Data and Mask arrays of the Search Engine.
The left half is filled first, then the right. Not all lo-
cations have to be filled.
SEARCH operations are performed twice, once on
the left half and then on the right half. Note that a
'1' in the Global Mask register enables a compare
during a SEARCH operation and a '0' forces a
match condition regardless of the state of the data
bit.
The SEARCH throughput for 34-bit operations is
half of the 68-bit operations. A search is performed
by using the Global Mask Register
“
0
”
for the left
half of the 68-bit, then another search is performed
using Global Mask Register 1 for the right half of
the 68-bit word. The order is important, as the left
half has a higher priority than the right half.
For example, if a search on the left half produces
a match and a search on the right half also produc-
es a match, then in that case, the left half is a high-
er priority. So if only one unique match exists in a
particular system, then a match on the left side
may alleviate the need to do a search on the right
half of the Data array.
Figure 15. Global Mask Register Patterns
Figure 16. Storing left half of a Data or Mask
Array
111
1000
0
000
0111
1
Register 0
Register 1
Bits
67
3433
0
AI04277
Bits
67
36 35
34
33
2
1 0
AI04278