參數(shù)資料
型號(hào)： MA180023
廠商： Microchip Technology
文件頁(yè)數(shù)： 172/228頁(yè)
文件大?。?/td> 0K
描述： MODULE PLUG-IN PIC18F46J11 PIM
產(chǎn)品培訓(xùn)模塊： PIC18 J Series MCU Overview
標(biāo)準(zhǔn)包裝： 1
系列： PIC®
附件類型： 插拔式模塊（PIM）- PIC18F46J11
適用于相關(guān)產(chǎn)品： HPC Explorer 板（DM183022）或 PIC18 Explorer 板（DM183032）
產(chǎn)品目錄頁(yè)面： 658 (CN2011-ZH PDF)
配用： DM183032-ND - BOARD EXPLORER PICDEM PIC18
DM183022-ND - BOARD DEMO PIC18FXX22 64/80TQFP
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PIC18F46J11 FAMILY
DS39932D-page 48
2011 Microchip Technology Inc.
TABLE 4-1:
LOW-POWER MODES
4.1.3
CLOCK TRANSITIONS AND STATUS
INDICATORS
The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Two bits indicate the current clock source and its
status:
OSTS
(OSCCON<3>)
and
T1RUN
(T1CON<6>). In general, only one of these bits will be
set in a given power-managed mode. When the OSTS
bit is set, the primary clock would be providing the
device clock. When the T1RUN bit is set, the Timer1
oscillator would be providing the clock. If neither of
these bits is set, INTRC would be clocking the device.
4.1.4
MULTIPLE SLEEP COMMANDS
The power-managed mode that is invoked with the
SLEEP
instruction is determined by the setting of the
IDLEN and DSEN bits at the time the instruction is exe-
cuted. If another SLEEP instruction is executed, the
device will enter the power-managed mode specified
by IDLEN and DSEN at that time. If IDLEN or DSEN
have changed, the device will enter the new
power-managed mode specified by the new setting.
4.2
Run Modes
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
4.2.1
PRI_RUN MODE
The PRI_RUN mode is the normal, full-power execu-
tion mode of the microcontroller. This is also the default
mode upon a device Reset unless Two-Speed Start-up
for details). In this mode, the OSTS bit is set (see
4.2.2
SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of low-power consumption while still using a
high-accuracy clock source.
SEC_RUN mode is entered by setting the SCS<1:0>
bits to ‘01’. The device clock source is switched to the
Timer1 oscillator (see Figure 4-1), the primary
oscillator is shut down, the T1RUN bit (T1CON<6>) is
set and the OSTS bit is cleared.
Mode
DSCONH<7>
OSCCON<7,1:0>
Module Clocking
Available Clock and Oscillator Source
DSEN(1)
IDLEN(1) SCS<1:0>
CPU
Peripherals
Sleep
00
N/A
Off
Timer1 oscillator and/or RTCC optionally enabled
Deep
Sleep(2)
10
N/A
Off
—
RTCC can run uninterrupted using the Timer1 or
internal low-power RC oscillator
PRI_RUN
0
N/A
00
Clocked
The normal, full-power execution mode. Primary clock
source (defined by FOSC<2:0>)
SEC_RUN
0
N/A
01
Clocked
Secondary – Timer1 oscillator
RC_RUN
0
N/A
11
Clocked
Postscaled internal clock
PRI_IDLE
01
00
Off
Clocked
Primary clock source (defined by FOSC<2:0>)
SEC_IDLE
01
Off
Clocked
Secondary – Timer1 oscillator
RC_IDLE
01
11
Off
Clocked
Postscaled internal clock
Note 1:
IDLEN and DSEN reflect their values when the SLEEP instruction is executed.
2:
Deep Sleep entirely shuts off the voltage regulator for ultra low-power consumption. See Section 4.6 “Deep
for more information.
Note:
Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep or Deep
Sleep mode, or one of the Idle modes,
depending on the setting of the IDLEN bit.
Note:
The Timer1 oscillator should already be
running prior to entering SEC_RUN
mode. If the T1OSCEN bit is not set when
the SCS<1:0> bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, device clocks will be delayed until
the oscillator has started. In such situa-
tions, initial oscillator operation is far from
stable and unpredictable operation may
result.
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