參數(shù)資料
型號： MA180023
廠商： Microchip Technology
文件頁數(shù)： 63/228頁
文件大小： 0K
描述： MODULE PLUG-IN PIC18F46J11 PIM
產(chǎn)品培訓(xùn)模塊： PIC18 J Series MCU Overview
標(biāo)準(zhǔn)包裝： 1
系列： PIC®
附件類型： 插拔式模塊（PIM）- PIC18F46J11
適用于相關(guān)產(chǎn)品： HPC Explorer 板（DM183022）或 PIC18 Explorer 板（DM183032）
產(chǎn)品目錄頁面： 658 (CN2011-ZH PDF)
配用： DM183032-ND - BOARD EXPLORER PICDEM PIC18
DM183022-ND - BOARD DEMO PIC18FXX22 64/80TQFP
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2010 Microchip Technology Inc.
DS70138G-page 155
dsPIC30F3014/4013
20.5
Watchdog Timer (WDT)
20.5.1
WATCHDOG TIMER OPERATION
The primary function of the Watchdog Timer (WDT) is
to reset the processor in the event of a software mal-
function. The WDT is a free-running timer that runs off
an on-chip RC oscillator, requiring no external compo-
nent. Therefore, the WDT timer continues to operate
even if the main processor clock (e.g., the crystal
oscillator) fails.
20.5.2
ENABLING AND DISABLING
THE WDT
The Watchdog Timer can be “Enabled” or “Disabled”
only through a Configuration bit (FWDTEN) in the
Configuration register, FWDT.
Setting FWDTEN = 1 enables the Watchdog Timer. The
enabling is done when programming the device. By
default, after chip erase, FWDTEN bit = 1. Any device
programmer
capable
of
programming
dsPIC30F
devices
allows
programming
of
this
and
other
Configuration bits.
If enabled, the WDT increments until it overflows or
“times out”. A WDT time-out forces a device Reset
(except during Sleep). To prevent a WDT time-out, the
user must clear the Watchdog Timer using a CLRWDT
instruction.
If a WDT times out during Sleep, the device wakes up.
The WDTO bit in the RCON register is cleared to
indicate a wake-up resulting from a WDT time-out.
Setting FWDTEN = 0 allows user software to enable/
disable the Watchdog Timer via the SWDTEN
(RCON<5>) control bit.
20.6
Low-Voltage Detect
The Low-Voltage Detect (LVD) module is used to
detect when the VDD of the device drops below a
threshold value, VLVD, which is determined by the
LVDL<3:0> bits (RCON<11:8>) and is thus user pro-
grammable. The internal voltage reference circuitry
requires a nominal amount of time to stabilize, and the
BGST bit (RCON<13>) indicates when the voltage
reference has stabilized.
In some devices, the LVD threshold voltage may be
applied externally on the LVDIN pin.
The LVD module is enabled by setting the LVDEN bit
(RCON<12>).
20.7
Power-Saving Modes
There are two power-saving states that can be entered
through the execution of a special instruction, PWRSAV;
these are Sleep and Idle.
The format of the PWRSAV instruction is as follows:
PWRSAV <parameter>
, where ‘parameter’ defines
Idle or Sleep mode.
20.7.1
SLEEP MODE
In Sleep mode, the clock to the CPU and peripherals is
shut down. If an on-chip oscillator is being used, it is
shut down.
The Fail-Safe Clock Monitor is not functional during
Sleep since there is no clock to monitor. However, the
LPRC clock remains active if WDT is operational during
Sleep.
The brown-out protection circuit and the Low-Voltage
Detect (LVD) circuit, if enabled, remains functional
during Sleep.
The processor wakes up from Sleep if at least one of
the following conditions has occurred:
any interrupt that is individually enabled and
meets the required priority level
any Reset (POR, BOR and MCLR)
WDT time-out
On waking up from Sleep mode, the processor restarts
the same clock that was active prior to entry into Sleep
mode.
When
clock
switching
is
enabled,
bits,
COSC<2:0>, determine the oscillator source to be
used on wake-up. If clock switch is disabled, then there
is only one system clock.
If the clock source is an oscillator, the clock to the
device is held off until OST times out (indicating a
stable oscillator). If PLL is used, the system clock is
held off until LOCK = 1 (indicating that the PLL is
stable). In either case, TPOR, TLOCK and TPWRT delays
are applied.
If EC, FRC, LPRC or ERC oscillators are used, then a
delay of TPOR (~ 10
s) is applied. This is the smallest
delay possible on wake-up from Sleep.
Moreover, if the LP oscillator was active during Sleep
and LP is the oscillator used on wake-up, then the start-
up delay is equal to TPOR. PWRT delay and OST timer
delay are not applied. In order to have the smallest
possible start-up delay when waking up from Sleep,
one of these faster wake-up options should be selected
before entering Sleep.
Note:
If a POR or BOR occurred, the selection of
the oscillator is based on the FOS<2:0>
and FPR<4:0> Configuration bits.
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