PIC18F46J11 FAMILY
DS39932D-page 6
2011 Microchip Technology Inc.
Pin Diagrams (Continued)
44-Pin QFN(1,3)
10
11
2
3
6
1
18
19
20 21 22
12 13
14 15
38
8
7
44
43
42 41
40 39
16 17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC18F4XJ11
37
RA3
/A
N
3
/V
RE
F
+/C1
INB
R
A
2/
A
N
2/V
RE
F-/
C
V
RE
F
-/C
2
IN
B
RA1
/AN1
/C2
IN
A/
P
M
A7
/RP1
RA
0
/AN0
/C
1I
N
A/
UL
P
W
U/
PM
A6
/RP0
MC
L
R
B
7/K
B
I3/
P
G
D
/RP1
0
R
B
6
/KBI
2/
PG
C/
RP9
RB5
/PM
A
0
/KBI
1/
RP
8
RB4
/P
M
A1
/KBI
0
/RP7
NC
R
C
6/
P
M
A5
/T
X1
/C
K
1/
RP1
7
RC
5/
S
D
O
1
/RP1
6
R
C
4/S
D
I1
/S
DA
1\
RP1
5
RD
3/
P
M
D
3/
RP2
0
RD
2/
P
M
D
2/
RP1
9
R
D
1/
PM
D1
/SDA2
R
D
0/
PM
D0
/SCL
2
R
C
3\
SCK1
/S
CL
1/
RP1
4
RC
2/
A
N
11
/C
T
P
L
S
/RP
3
R
C
1/T
1OS
I/
RP1
2
RC0/T
1O
S
O
/T
1CK
I/
RP1
1
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VSS
AVDD
RE2/AN7/PMCS
RE1/AN6/PMWR
RE0/AN5/PMRD
RA5/AN4/SS1/HLVDIN/RP2
VDDCORE/VCAP(2)
RC7/PMA4/RX1/DT1/RP18
RD4/PMD4/RP21
RD5/PMD5/RP22
RD6/PMD6/RP23
VSS
VDD
RB0/AN12/INT0/RP3
RB1/AN10/PMBE/RTCC/RP4
RB2/AN8/CTED1/PMA3/REFO/RP5
RB
3
/AN9
/CTED2
/P
M
A2
/RP6
RD7/PMD7/RP24
5
4
AVSS
VDD
AVDD
Legend:
RPn
represents remappable pins.
Note
1:
Some input and output functions are routed through the Peripheral Pin Select (PPS) module and can be
dynamically assigned to any of the RPn pins. For a list of the input and output functions, see
Table 10-13.
2:
3:
For the QFN package, it is recommended that the bottom pad be connected to VSS.
= Pins are up to 5.5V tolerant