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參數(shù)資料
| 型號(hào)： | MA31750 |
| 廠商： | Dynex Semiconductor Ltd. |
| 英文描述： | High Performance MIL-STD-1750 Microprocessor |
| 中文描述： | 高性能的MIL - STD - 1750微處理器 |
| 文件頁(yè)數(shù)： | 12/42頁(yè) |
| 文件大?。?/td> | 436K |
| 代理商： | MA31750 |
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MA31750
12/42
Figure 16: Data Formats
Single Precision Fixed-Point
MSB
Byte
MSB
Double-Precision Fixed-Point
MSB
Floating Point
MSB
Extended Precision Floating Point
MSB
Value
0
15
Mantissa (Most significant)
Mantissa (Least Sig.)
Exponent
0
23 24
31 32
47
Mantissa
Exponent
0
23
31
Upper byte
Lower byte
0
15
Unsigned value
0
31
Value
0
31
Unsigned value
0
15
Unsigned Double Precision Fixed-Point (1750B)
MSB
Unsigned Single Precision Fixed-Point (1750B)
MSB
LSB MSB
LSB
LSB
LSB
LSB
LSB
LSB MSB
LSB
LSB MSB
LSB MSB
LSB
Note:
All values are
Signed 2s complement
unless shown as
unsigned.
24
Mode
R
D, DX
Name
Register Direct
Memory Direct
Derived Operand
The operand is contained in a regular specified by the instruction.
The instruction postword (plus RX if RX
≠
0), contains the memory address of the
operand.
The instruction postword (plus RX if RX
≠
0) contains the address of the address
which holds the operand.
The instruction postword (plus RX if RX
≠
0) holds the operand.
The operand value is specified as part of the instruction. (ISP specifies values
between 0001H and 0010H, ISN specifies values between FFFFH and FFEFH).
The operand value is specified as part of the instruction. (ISP specifies values
between 0001n and 0010n, ISN specifies values between FFFFn and FFEFn).
A 2s-complement, 8-bit displacement which is sign-extended and added to the
Instruction counter to provide an offset of -128 to +127.
Data at address given by: contents of specified base register (R12-R15, specified
by opcode), plus unsigned 8-bit displacement field from opcode.
Data at address given by contents of specified base register (R12-R15, specified
by opcode), plus contents of RX register if RX
≠
R0
See instruction for details.
I, IX
Memory Indirect
IM, IMX
ISP
Immediate Long
Immediate Short Positive
ISN
Immediate Short Negative
ICR
Instruction Counter
Relative
Base Relative
B
BX
Base Relative Indexed
S
Special
Figure 17: Address Mode Summary
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MA31751 | Memory Management & Block Protection Unit |
| MA31753 | DMA Controller (DMAC) For An MA31750 System |
| MA31755 | 16-Bit Feedthrough Error Detection & Correction Unit EDAC |
| MA3690 | 1553B Bus Controller/Remote Terminal |
| MA3691 | 1553B Bus Controller/Remote Terminal |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MA31751 | 制造商:DYNEX 制造商全稱:Dynex Semiconductor 功能描述:Memory Management & Block Protection Unit |
| MA31753 | 制造商:DYNEX 制造商全稱:Dynex Semiconductor 功能描述:DMA Controller (DMAC) For An MA31750 System |
| MA31755 | 制造商:DYNEX 制造商全稱:Dynex Semiconductor 功能描述:16-Bit Feedthrough Error Detection & Correction Unit EDAC |
| MA318 | 功能描述:CPU與芯片冷卻器 INTEL P111 FC-PGA RoHS:否 制造商:ADLINK Technology 尺寸: 電壓額定值: 功率額定值: 速度: 氣流: 系列: |
| MA3180 | 制造商:PANASONIC 制造商全稱:Panasonic Semiconductor 功能描述:Silicon planar type |
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