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參數(shù)資料
| 型號： | MA31750 |
| 廠商： | Dynex Semiconductor Ltd. |
| 英文描述： | High Performance MIL-STD-1750 Microprocessor |
| 中文描述： | 高性能的MIL - STD - 1750微處理器 |
| 文件頁數(shù)： | 3/42頁 |
| 文件大?。?/td> | 436K |
| 代理商： | MA31750 |
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MA31750
3/42
3. MODES OF OPERATION
MA31750 operating modes include: (1) initialisation, (2)
instruction execution, (3) interrupt servicing, (4) fault servicing,
(5) timer operations and (6) console operation.
3.1. INITIALISATION
The MA31750 executes a microcoded initialisation routine
in response to a hardware reset or power-up. Figure 3 shows
a cycle-by-cycle breakdown of this routine. The operations
performed are dependent on the system configuration read by
the processor during startup. Figure 2 summarises the
resulting initialisation state.
The last action performed by the initialisation routine is to
load the instruction pipeline. Instruction fetches start at
memory location zero with AS = 0, PS = 0 and PB = 0 and will
be from the Start-Up ROM (SUR) if implemented. Whether
BIT passes or not, the processor will begin instruction
execution at this point. The system start-up code may include
a routine to enable and unmask interrupts in order to detect
and respond to a BIT failure if required.
Addr
0
1
*2
Operation
PIC initialised
A<-- 0x8410
Read external configuration register from 8410H
(CONFWN asserted low)
-
-
If BPU, N<-- 128 else N<-- 0
Decrement N; branch to 21 if N >= 0
Write internal configuration register
-
If no MMU, br to 7
-
-
N <-- 256
Decrement N
Write MMU Instruction Page Register N
Write MMU Operand Page Register N; branch to 16 if
N > 0
A <-- 0400H
N <-- 16
PBSR <-- N
-
Write Memory control register to MMU with PB = N
Decrement N; branch if N >= 0 to 1B
A <-- 0
IC <-- A
Br to BIT if required
-
Br if no SUR to 00D
-
Re-init PIC
-
Zero SW
-
-
Br to 011 if BIT passed (or not run)
3
1F
20
21
4
5
6
13
14
15
16
*17
*18
19
1A
1B
1C
*1D
1E
7
8
9
A
B
C
D
E
*F
10
32
33
34
35
36
11
12
*3F8
*3F9
Set FT bit 13
Init DMAE, SUREN, NPU
Fetch first word from 0
Fetch second word from 1
First instruction first cycle
* Indicates an external cycle
Figure 3: Initialization Sequence
Figure 2: Initialization State
MA31750
Instruction Counter
Status Word
Fault Register Zero
Fault Mask Register (1750B)
Pending Interrupt Register
Interrupt Mask Register
General Registers
Interrupts
Timers A and B
Timer Reset Registers (1750B)
Trigger-Go Counter
TGON Line
Start-Up ROM
DMA
Zero
Zero
Zero
All ones
Zero
Zero
Undefined
Disabled
Zeroed and started
Zero
Reset and started
High
Enabled
Disabled
MMU
Page Registers AL/W/E fields
Page Register PPA field
Zero
Logical to physical
BPU
Memory Protect RAM
Global Memory Protect
Zero (disabled)
Enabled
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MA31751 | Memory Management & Block Protection Unit |
| MA31753 | DMA Controller (DMAC) For An MA31750 System |
| MA31755 | 16-Bit Feedthrough Error Detection & Correction Unit EDAC |
| MA3690 | 1553B Bus Controller/Remote Terminal |
| MA3691 | 1553B Bus Controller/Remote Terminal |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MA31751 | 制造商:DYNEX 制造商全稱:Dynex Semiconductor 功能描述:Memory Management & Block Protection Unit |
| MA31753 | 制造商:DYNEX 制造商全稱:Dynex Semiconductor 功能描述:DMA Controller (DMAC) For An MA31750 System |
| MA31755 | 制造商:DYNEX 制造商全稱:Dynex Semiconductor 功能描述:16-Bit Feedthrough Error Detection & Correction Unit EDAC |
| MA318 | 功能描述:CPU與芯片冷卻器 INTEL P111 FC-PGA RoHS:否 制造商:ADLINK Technology 尺寸: 電壓額定值: 功率額定值: 速度: 氣流: 系列: |
| MA3180 | 制造商:PANASONIC 制造商全稱:Panasonic Semiconductor 功能描述:Silicon planar type |
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