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參數(shù)資料
| 型號： | MAX1358BETL+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 25/71頁 |
| 文件大小： | 0K |
| 描述： | IC DAS 16BIT 40-TQFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS） |
| 分辨率（位）： | 16 b |
| 采樣率（每秒）： | 21.94k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 1.8 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 40-TQFN-EP（6x6） |
| 包裝： | 帶卷 (TR) |
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MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
______________________________________________________________________________________
31
Watchdog
Enable the watchdog timer by writing a 1 to the WDE
bit in the CLK_CTRL register. After enabling the watch-
dog timer, the device asserts
RESET for 250ms, if the
watchdog address register is not written every 500ms.
Due to the asynchronous nature of the watchdog timer,
the watchdog timeout period varies between 500ms
and 750ms. Write a 0 to the WDE bit to disable the
watchdog timer. See Figure 11 for a block diagram of
the watchdog timer.
High-Frequency Clock
An internal oscillator and an FLL are used to generate a
4.9152MHz ±1% high-frequency clock. This clock and
derivatives are used internally by the ADC, analog
switches, and PWM. This clock signal outputs to CLK.
When the FLL is enabled, the high- frequency clock is
locked to the 32.768kHz reference. If the FLL is dis-
abled, the high-frequency clock is free-running. At
power-up, the CLK pin defaults to a 2.4576MHz clock
output, which is compatible with most Cs. See Figure
12 for a block diagram of the high-frequency clock.
User-Programmable I/Os
The MAX1358B provides four digital programmable
I/Os (UPIO1–UPIO4). Configure UPIOs as logic inputs
or outputs using the UPIO control register. Configure
the internal pullups using the UPIO setup register, if
required. At power-up, the UPIOs are internally pulled
up to DVDD. UPIO_ outputs can be referenced to DVDD
or CPOUT. See the
UPIO__CTRL Register and
UPIO_SPI Register sections for more details on config-
uring the UPIO_ pins.
32KIN
32KOUT
32.768kHz OSCILLATOR
32kHz
OSCILLATOR
OSCE
32K
Figure 9. 32kHz Crystal-Oscillator Block Diagram
IO32E
CLK32K
CK32E
OSCE
CLK32K I/O CONTROL
2:1
MUX
1
0
IO32E
32K
M32K
Figure 10. CLK32K I/O Block Diagram
D
Q
R
CK
D
Q
R
CK
DIVIDE-
BY-8192
32K
WDE
POR
WDW
WATCHDOG TIMER
POR PULSES HIGH DURING POWER-UP.
WDW PULSES HIGH DURING WATCHDOG REGISTER WRITE.
4Hz
WDTO
Figure 11. Watchdog Timer Block Diagram
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