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參數(shù)資料
| 型號(hào)： | MAX1358BETL+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 35/71頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DAS 16BIT 40-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS） |
| 分辨率（位）： | 16 b |
| 采樣率（每秒）： | 21.94k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 1.8 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 40-TQFN-EP（6x6） |
| 包裝： | 帶卷 (TR) |
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MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
40
______________________________________________________________________________________
OFFSET<23:0>: Offset-calibration bits. The data format
is two’s complement and is subtracted from the ADC
output before being written to the DATA register. The
offset calibration allows input offset errors between
VREF ±50% to be corrected in unipolar or bipolar mode.
The MAX1358B can perform system offset calibration
or self-offset calibration. Self-calibration performs a cal-
ibration for the entire signal path. See the
ADC
Calibration section for more details.
The ADC input voltage range specifications must
always be obeyed, and the OFFSET CAL register effec-
tively offsets the ADC digital scale to a “zero” value
determined by the calibration.
MSB
ADC15
ADC14
ADC13
ADC12
ADC11
ADC10
ADC9
ADC8
LSB
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
DATA Register (Power-On State: 0000 0000 0000 0000)
ADC<15:0> Analog-to-digital conversion data bits.
These 16 bits are the results from the most recently
completed conversion. The data format is unsigned,
binary for unipolar mode, and two’s complement for
bipolar mode.
MSB
OFFSET23
OFFSET22
OFFSET21
OFFSET20
OFFSET19
OFFSET18
OFFSET17
OFFSET16
OFFSET15
OFFSET14
OFFSET13
OFFSET12
OFFSET11
OFFSET10
OFFSET9
OFFSET8
LSB
OFFSET7
OFFSET6
OFFSET5
OFFSET4
OFFSET3
OFFSET2
OFFSET1
OFFSET0
OFFSET CAL Register (Power-On State: 0000 0000 0000 0000 0000 0000)
MSB
GAIN23
GAIN22
GAIN21
GAIN20
GAIN19
GAIN18
GAIN17
GAIN16
GAIN15
GAIN14
GAIN13
GAIN12
GAIN11
GAIN10
GAIN9
GAIN8
LSB
GAIN7
GAIN6
GAIN5
GAIN4
GAIN3
GAIN2
GAIN1
GAIN0
GAIN CAL Register (Power-On State: 1000 0000 0000 0000 0000 0000)
GAIN<23:0>: Gain-calibration bits. The data format is
unsigned binary with 23 bits to the right of the decimal
point and scales the ADC output before being written to
the DATA register. The gain calibration allows full-scale
errors between -VREF/2 and +VREF/2 to be corrected in
unipolar mode and full-scale errors between (+50% x
VREF) and (+200% x VREF) in unipolar or bipolar mode.
The MAX1358B can perform system gain calibration or
self-gain calibration. Self-calibration performs a calibra-
tion for offsets in the ADC, and system calibration per-
forms a calibration for the entire signal path. See the
ADC Calibration section for more details.
The ADC input voltage range specifications must always
be obeyed, and the GAIN CAL register effectively scales
the ADC digital output to a full-scale value determined
by the calibration. The usable gain-calibration range is
limited to less than the full GAIN CAL register digital-
scaling range by the internal noise of the ADC.
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