參數資料
| 型號： | MAX1358BETL+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 49/71頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS 16BIT 40-TQFN |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 類型： | 數據采集系統(tǒng)（DAS） |
| 分辨率（位）： | 16 b |
| 采樣率（每秒）： | 21.94k |
| 數據接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 電壓電源： | 模擬和數字 |
| 電源電壓： | 1.8 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 40-TQFN-EP（6x6） |
| 包裝： | 帶卷 (TR) |
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MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
______________________________________________________________________________________
53
UP4MD<3:0>,
UP3MD<3:0>,
UP2MD<3:0>, UP1MD<3:0>
MODE
DESCRIPTION
0
GPI
General-purpose digital input. Active edges detected by UPR_ or UPF_
status register bits. ALH_ has no effect with this setting.
0
1
GPO
General-purpose digital output. Logic level set by LL_ bit. ALH_ has no
effect with this setting.
0
1
0
SWA or
SWA
Digital input. DAC A buffer switch control. See the SWA bit description in
the SW_CTRL Register section.
0
1
SWB or
SWB
Digital input. DAC B buffer switch control. See the SWB bit description in
the SW_CTRL Register section.
0
1
0
SPDT1 or
SPDT1
Digital input. SPDT1 switch control. See the SPDT1<1:0> bit description in the
SW_CTRL Register section.
0
1
0
1
SPDT2 or
SPDT2
Digital input. SPDT2 switch control. See the SPDT2<1:0> bit description in the
SW_CTRL Register section.
0
1
0
SLEEP or
SLEEP
Sleep-mode digital input. Overrides power-control register and puts the
part into sleep mode when asserted. The clock buffers must be powered
down separately. When deasserted, power mode is determined by the
SHDN bit.
0
1
WU or
WU
Wake-up digital input. Asserted edge clears SHDN bit.
1
0
1
0
1
0
1
0
Reserved
Reserved. Do not use these settings.
1
0
1
PWM or
PWM
PWM digital output. Signal defined by the PWM_CTRL register. PWM on
(or high or “1”); assertion level defined by the ALH_ bit. When PWM is
disabled (PWME = 0), the UPIO pin idles high (DVDD or CPOUT) if
ALH = 1, and low (DGND) if ALH = 0.
1
0
SHDN or
SHDN
Power-supply shutdown digital output. Equivalent to SHDN bit. Power-on
default of GPI with pullup ensures initial power-supply turn-on when UPIO
is connected to a power supply with a
SHDN input.
1
0
1
AL_DAY or
AL_DAY
RTC alarm digital output. Asserts for time-of-day alarm events; equivalent
to ALD in STATUS register.
1
0
Reserved
Reserved. Do not use these settings.
1
DRDY or
DRDY
ADC data-ready digital output. Asserts when analog-to-digital conversion
or calibration completes. Not masked by MADD bit.
Table 16. UPIO Mode Configuration
Note: When multiple UPIO inputs are configured for the same input function, the inputs are ORed together.
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