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參數(shù)資料
| 型號： | MAX1358BETL+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 32/71頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS 16BIT 40-TQFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS） |
| 分辨率（位）： | 16 b |
| 采樣率（每秒）： | 21.94k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 1.8 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 40-TQFN-EP（6x6） |
| 包裝： | 帶卷 (TR) |
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MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
38
______________________________________________________________________________________
RATE<2:0>: ADC conversion-rate-setting bits. These
three bits set the conversion rate of the ADC as shown
in Table 6. The initial conversion requires four conver-
sion cycles for valid data, and subsequent conversions
require only one cycle (if CONT = 1). A full-scale input
change can require up to five cycles for valid data if
the digital filter is not reset with the STRT or S bit.
MODE<2:0>: Conversion-mode bits. These three bits
determine the type of conversion for the ADC as shown
in Table 7. When the ADC finishes an offset calibration
and/or gain calibration, the MODE<2:0> bits clear to 0
hex, the ADD bit in the STATUS register asserts, and
an interrupt asserts on INT (or UPIO_ if programmed as
DRDY) if MADD is unmasked. Perform a gain calibra-
tion after achieving the desired offset (calibrated or
not). If an offset and gain calibration are performed
together (MODE<2:0> = 7 hex), the offset calibration is
performed first followed by the gain calibration, and the
C is interrupted by INT (or UPIO_ if programmed as
DRDY) if MADD is unmasked only upon completion of
both offset and gain calibration. After power-on or cali-
bration, the ADC does not begin conversions until initi-
ated by the user (see the ADCE and STRT bit
descriptions in this section and see the S bit descrip-
tions in the
MUX Register section). See the GAIN CAL
Register and OFFSET CAL Register sections for details
on system calibration.
CONVERSION MODE
MODE2
MODE1
MODE0
Normal
0
System Offset Calibration
0
1
System Gain Calibration
0
1
0
Normal
0
1
Normal
1
0
Self-Offset Calibration
1
0
1
Self-Gain Calibration
1
0
Self-Offset and Gain
Calibration
1
Table 7. Setting the ADC Conversion Mode
NOMINAL
CONTINUOUS
CONVERSION
RATE (sps)
DECIMATION
RATIO
ACTUAL
CONTINUOUS
CONVERSION
RATE (sps)
10
1096
10.01
40
274
40.04
50
220
49.87
60
183
59.95
200
55
199.48
240
46
238.51
400
27
406.35
477
23
477.02
CONTINUOUS
CONVERSION
RATE (sps)
SINGLE
CONVERSION
RATE (sps)
RATE2
RATE1
RATE0
10
2.5
0
40
10
0
1
50
12.5
0
1
0
60
15
0
1
200
50
1
0
240
60
1
0
1
400
100
1
0
477
128
1
Table 6a. Setting the ADC Conversion Rate*
*Calculate the ADC sampling rate using the following
equation:
where fHFCLK = 4.9152MHz nominally.
f
decimation ratio
S
HFCLK
=
×
448
Table 6b. Actual ADC Conversion Rates
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