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參數(shù)資料
| 型號： | MB86960 |
| 廠商： | Fujitsu Limited |
| 英文描述： | NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE) |
| 中文描述： | 網(wǎng)絡(luò)接口控制器的編碼/解碼器（尼斯） |
| 文件頁數(shù)： | 26/65頁 |
| 文件大?。?/td> | 488K |
| 代理商： | MB86960 |
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MB86960
Receive Interrupt Enable Register
This register provides control for enabling or masking
interrupts based on the assertion of status bits in DCLR1,
the Receive Status Register. See Table 7.
Transmit Mode Register
This register contains two control bits associated with
transmission, a general-purpose control bit which drives
a pin on the chip, and a collision counter. See Table 9.
Table 7. DLCR3 — Receive Interrupt Enable Register
BIT
SYMBOL
TYPE
DESCRIPTION
7
INT EN
R
W
0
INTERRUPT ENABLE:
When high, enables RX PKT to generate interrupt.
See also DLCR1<7>.
6
INT EN
R
W
0
INTERRUPT ENABLE:
When high, enables BUS RD ERR to generate interrupt.
See also DLCR1<6>.
5
INT EN
R
W
0
INTERRUPT ENABLE:
When high, enables DMA EOP to generate interrupt.
See also DLCR1<5>.
4
INT EN
R
W
0
INTERRUPT ENABLE:
When high, enables RMT 0900H to generate interrupt.
See also DLCR1<4>.
3
INT EN
R
W
0
INTERRUPT ENABLE:
When high, enables SHORT ERR to generate interrupt.
See also DLCR1<3> and Table 8.
2
INT EN
R
W
0
INTERRUPT ENABLE:
When high, enables ALIGN ERR to generate interrupt.
See also DLCR1<2> and Table 8.
1
INT EN
R
W
0
INTERRUPT ENABLE:
When high, enables CRC ERR to generate interrupt.
See also DLCR1<1> and Table 8.
0
INT EN
R
W
0
INTERRUPT ENABLE:
When high, enables RBUF OVRFLO to generate interrupt.
See also DLCR1<0>.
Table 8. Network Error Monitoring Modes
ACPT BAD
PKTS
DLCR5<5>
ACPT
SHORT
PKTS
DLCR5<3>
INT EN
SHORT
ERRORS
DLCR3<3>
INT EN
ALIGN
ERRORS
DLCR3<2>
INT EN CRC
ERRORS
DLCR3<1>
Mode
Description
0
0
0
0
0
Normal non-monitor mode.
0
0
1/0
1/0
1/0
Error interrupts only, if enabled.
0
1
0
1/0
1/0
Save short packets if otherwise error free in buffer;
interrupts only for alignment and CRC errors, if
enabled. RX PKT will be set high if short packet
received.
1
0
0
0
0
Save packets with short, alignment and/or CRC
errors in buffer; RX PKT will be set high if packet
with error received.
All others
Do Not Use.
Note: Packet acceptance requires both error filter acceptance and address filter acceptance.
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| MB86960APF-G | NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE) |
| MB86961A | UNIVERSAL INTERFACE FOR 10BASET |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB86960APF-G | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE) |
| MB86961A | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:UNIVERSAL INTERFACE FOR 10BASET |
| MB86961APD-G | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:UNIVERSAL INTERFACE FOR 10BASET |
| MB86961APF-G | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:UNIVERSAL INTERFACE FOR 10BASET |
| MB86965 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER |
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