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參數(shù)資料
| 型號(hào)： | MB86960 |
| 廠(chǎng)商： | Fujitsu Limited |
| 英文描述： | NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE) |
| 中文描述： | 網(wǎng)絡(luò)接口控制器的編碼/解碼器（尼斯） |
| 文件頁(yè)數(shù)： | 30/65頁(yè) |
| 文件大小： | 488K |
| 代理商： | MB86960 |
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MB86960
Table 13. DLCR7 — Configuration Register 1
BIT
SYMBOL
TYPE
DESCRIPTION
7, 6
E/D
CNF
1,0
R
W
00
ENCODER/DECODER CONFIGURATION:
Selects the operating mode of the
controller-encoder/decoder functions and their interface. See table below and pin
descriptions for the monitor pins, TXD, TCK, TEN, LBC, RXD, RCK, CRS and COL:
E/D CNF 1
E/D CNF 0
Registers
0
0
Normal NICE:
Internal encoder/decoder active.
Monitor pins inactive.
0
1
NICE + Monitor:
Internal encoder/decoder active.
Monitor pins outputting all controller/encoder/
decoder interface signals
1
0
Encoder/Decoder Bypass:
Internal encoder/
decoder not used. Monitor pins can be used to
interface controller to external encoder/decoder.
1
1
Encoder/Decoder Test:
Controller inactive,
encoder/decoder active. Monitor pins used to test
encoder/decoder.
5
PWRDN
R
W
1
POWER DOWN:
When set high, enables power to the chip for all functions; when set low,
places chip in power down mode for power conservation.
4
RDYPOL
R
0/1
READY PIN POLARITY:
Reads the state of the RDY POL pin 94.
3, 2
RBS 1, 0
R
W
00
REGISTER BANK SELECT:
Provides the indirect address for selection of one of the three
sets of registers to access when the physical register address is xxx8H–xxxFH.
The lower 7 registers are not bank-selectable. See table:
RBS1
RBS0
Registers
0
0
DLCR0-7, DLCR8-F
0
1
DLCR0-7, HT8-F
1
0
DLCR0-7, BMR8-F
1
1
RESERVED
1
EOPPOL
R
W
0
EOP PIN SIGNAL POLARITY:
When high, the EOP pin is active-high; when low, EOP is
active-low.
0
M..L/
L..M
R
W
0
BYTE ORDER CONTROL:
Selects byte lane ordering for packet data in the buffer (applies
only n System Word Mode). In both Most..Least and Least..Most modes, the first and second
bytes of the packet will appear in the same word on the system bus. When this bit is high (M..L
mode), the first and all odd-numbered bytes of a packet and its header will appear on the high
byte of the system bus. Note that header bytes are also swapped.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MB86960APF-G | 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE) |
| MB86961A | 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:UNIVERSAL INTERFACE FOR 10BASET |
| MB86961APD-G | 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:UNIVERSAL INTERFACE FOR 10BASET |
| MB86961APF-G | 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:UNIVERSAL INTERFACE FOR 10BASET |
| MB86965 | 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER |
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