參數(shù)資料
型號(hào)： MB86960
廠商： Fujitsu Limited
英文描述： NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE)
中文描述： 網(wǎng)絡(luò)接口控制器的編碼/解碼器（尼斯）
文件頁(yè)數(shù)： 6/65頁(yè)
文件大小： 488K
代理商： MB86960
MB86960
PIN DESCRIPTIONS
Buffer Memory Interface Pins
SYMBOL
TYPE
DESCRIPTION
BCS0
BSC1
O
O
BUFFER CHIP SELECT:
BCS1 and BSC0 are the chip select lines, most significant byte and least
significant byte respectively, of the dedicated buffer SRAMs, Active low.
BOE
O
BUFFER OUTPUT ENABLE:
This active low signal is the output enable for the Buffer SRAM, and
is asserted by NICE during buffer memory read cycles.
BWE
O
BUFFER WRITE ENABLE:
Active low. Used as a write strobe to the buffer SRAM memory during
write operations.
BD<15:0>
B
B
BUFFER DATA:
Data lines between the SRAM buffer memory and NICE. This SRAM data bus is
configurable for an 8-bit or 16-bit data size by BUFFER BYTE/BUFFER WORD, BB/BW, in
DLCR6<4>. The transfer byte order within a word, most significant or least-significant byte first, is
determined by DATA_ORDER, DLCR7<1>.
BA<15:0>
O
O
BUFFER ADDRESS:
These lines address up to 64 kilobytes of SRAM buffer memory.
Network Interface Pins
SYMBOL
TYPE
DESCRIPTION
TXDATA+
TXDATA–
O
O
TRANSMIT INTERFACE PAIR:
These are the differential outputs to the transceiver for transmitting.
RXDATA+
RXDATA–
I
I
RECEIVED DATA:
These are the Manchester differential inputs from the transceiver to the receiver.
COL+
COL–
I
I
COLLISION:
These differential nputs are driven with a 10 MHz signal when the transceiver detects a
collision on the media.
AC/DC
I
AC/DC COUPLING SELECT:
AC/DC = 1 selects AC coupling; 0 selects DC coupling for the
TXDATA
±
outputs. When AC coupling is selected, both TXDATA+ and TXDATA– are driven to the
same output voltage level during the transmit idle period to prevent saturation of the isolation
transformer. With DC coupling, these outputs remain at a 1 level during idle periods.
System Clock Pins
SYMBOL
TYPE
DESCRIPTION
X1
I
CRYSTAL INPUT:
Connection for one side of the 20 MHz crystal, or input for an external 20 MHz
clock source.
X2
O
CRYSTAL OUTPUT:
Connection for the other side of the 20 MHz crystal. Leave unconnected if an
external clock is used.
CKOUT
O
CLOCK OUTPUT:
20 MHz free-running clock output provided by the crystal
oscillator circuit.
相關(guān)PDF資料
PDF描述
MB86960APF-G NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE)
MB86961A UNIVERSAL INTERFACE FOR 10BASET
MB86961APD-G UNIVERSAL INTERFACE FOR 10BASET
MB86961APF-G UNIVERSAL INTERFACE FOR 10BASET
MB86965 EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MB86960APF-G 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE)
MB86961A 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:UNIVERSAL INTERFACE FOR 10BASET
MB86961APD-G 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:UNIVERSAL INTERFACE FOR 10BASET
MB86961APF-G 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:UNIVERSAL INTERFACE FOR 10BASET
MB86965 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER
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