參數(shù)資料
型號: MB91110PMT2
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP144
封裝: PLASTIC, LQFP-144
文件頁數(shù): 26/94頁
文件大?。?/td> 1099K
代理商: MB91110PMT2
MB91110 Series
32
(Continued)
*1 : ICR sets the interruption level for each interruption request using the register built into the interruption controller.
ICR is prepared in accordance with each interruption request.
*2 : TBR is the register that indicates the starting address of the vector table for EIT.
Addresses with added offset values that are specified per TBR and EIT factor will be the vector addresses.
*3 : REALOS OS/FR uses 0X40, 0X41 interruptions for system codes.
Reference :
The vector area for EIT is 1 KB in accordance with the address shown by TBR.
The size per vector is 4 bytes, and the relationship between the vector numbers and their addresses is shown
as follows.
Interruption source
Interruption number
Interruption
level *1
Offset
Interruption vector
address to TBR of
default *2
Decimal
Hexadeci-
mal
System reservation
(used under REALOS) *3
65
41
2F8H
000FFEF8H
Used under INT instruction
66
to
255
42
to
FF
2F4H
to
000H
000FFEF4H
to
000FFD00H
vctadr
= TBR + vctofs
= TBR + (3FCH 4 × vct)
vctadr : vector address
vctofs : vector offset
vct : vector number
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