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參數(shù)資料
| 型號： | MB91110PMT2 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 93/94頁 |
| 文件大?。?/td> | 1099K |
| 代理商： | MB91110PMT2 |
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97
Atmel ATmega16/32/64/M1/C1 [DATASHEET]
7647K–AVR–12/13
13.4
Counter Unit
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 13-2 shows a block
diagram of the counter and its surroundings.
Figure 13-2. Counter Unit Block Diagram
Signal description (internal signals):
Count
Increment or decrement TCNTn by 1.
Direction
Select between increment and decrement.
Clear
Clear TCNTn (set all bits to zero).
clkTn
Timer/Counter clock.
TOP
Signalize that TCNTn has reached maximum value.
BOTTOM
Signalize that TCNTn has reached minimum value (zero).
RTG
An external event (ICP1A or ICP1B) asks for a TOP like action.
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) containing the upper eight bits of the
counter, and Counter Low (TCNTnL) containing the lower eight bits. The TCNTnH Register can only be indirectly accessed by
the CPU. When the CPU does an access to the TCNTnH I/O location, the CPU accesses the high byte temporary register
(TEMP). The temporary register is updated with the TCNTnH value when the TCNTnL is read, and TCNTnH is updated with the
temporary register value when TCNTnL is written. This allows the CPU to read or write the entire 16-bit counter value within one
clock cycle via the 8-bit data bus. It is important to notice that there are special cases of writing to the TCNTn register when the
counter is counting that will give unpredictable results. The special cases are described in the sections where they are of
importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkTn). The
clkTn can be generated from an external or internal clock source, selected by the Clock Select bits (CSn2:0). When no clock
source is selected (CSn2:0 = 0) the timer is stopped. However, the TCNTn value can be accessed by the CPU, independent of
whether clkTn is present or not. A CPU write overrides (has priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits (WGMn3:0) located in the
Timer/Counter Control Registers
A and B (TCCRnA and TCCRnB). There are close connections between how the counter
behaves (counts) and how waveforms are generated on the output compare outputs OCnx. For more details about advanced
counting sequences and waveform generation, see Section 13. “16-bit Timer/Counter1 with PWM” on page 92.
The Timer/Counter overflow flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be
used for generating a CPU interrupt.
BOTTOM
RTG
TOP
TOVn
(Int. Req.)
DATA BUS (8-bit)
Control Logic
TCNTnH (8-bit)
TCNTnH (16-bit Counter)
TCNTnL (8-bit)
TEMP (8-bit)
clkTn
Clear
Count
Direction
Edge
Detector
(From Prescaler)
Clock Select
Tn
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MB911110PMT2 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-Bit RISC Microcontroller |
| MB91121 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit RISC Microcontroller |
| MB91121PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit RISC Microcontroller CMOS |
| MB91133 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-Bit RISC Microcontroller |
| MB91133PBT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-Bit RISC Microcontroller |
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