參數(shù)資料
型號: MB91110PMT2
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP144
封裝: PLASTIC, LQFP-144
文件頁數(shù): 70/94頁
文件大小: 1099K
代理商: MB91110PMT2
76
Atmel ATmega16/32/64/M1/C1 [DATASHEET]
7647K–AVR–12/13
Figure 11-2. Prescaler for Timer/Counter0 and Timer/Counter1(1)
Note:
1.
The synchronization logic on the input pins (
Tn) is shown in Figure 11-1.
11.3.1 General Timer/Counter Control Register – GTCCR
Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter synchronization mode. In this mode, the value that is written to the
PSRSYNC bit is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding
Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during
configuration. When the TSM bit is written to zero, the PSRSYNC bit is cleared by hardware, and the Timer/Counters start
counting simultaneously.
Bit6 – ICPSEL1: Timer 1 Input Capture Selection
Timer 1 capture function has two possible inputs ICP1A (PD4) and ICP1B (PC3). The selection is made thanks to ICPSEL1 bit
as described in Table 11-1.
Bit 0 – PSRSYNC: Prescaler Reset
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by
hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of
this prescaler will affect both timers.
Timer/Counter1 Clock Source
clkT1
clkI/O
PSRSYNC
T0
10-bit T/C Prescaler
0
CS10
CK/8
CK/64
CK/256
CK/1024
CS11
CS12
Synchronization
Clear
T1
Synchronization
Timer/Counter0 Clock Source
clkT0
0
CS00
CS01
CS02
Bit
7
6
543
2
1
0
TSM
ICPSEL1
PSRSYNC
GTCCR
Read/Write
R/W
R
R/W
Initial Value
0
Table 11-1. ICPSEL1
ICPSEL1
Description
0
Select ICP1A as trigger for timer 1 input capture
1
Select ICP1B as trigger for timer 1 input capture
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