Functional Description
MOTOROLA
MC13180
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During the Config state, any address location can be read or written. The Sleep Enable, Tx Enable, and Rx
Enable bits of the register map must remain at a logic zero, otherwise the register map is typically loaded
with user defined default values.
4.7 WAIT XTAL State
During this state, the crystal oscillator and data clock PLL are stabilizing. If an external reference oscillator
is being used, the data clock PLL must still be allowed to settle. Stability will be achieved after T
WAIT
, at
which time the Idle state is entered.
4.8 IDLE State
In the Idle state, the CLK output supplies a synthesized 24 MHz output. Any SPI operation is allowed
during this state. RSSI information is typically read during the Idle state.
4.9 TX CONFIG State
During this state, the contents of the register map are set for any desired transmit information, including the
transmit channel setting. The Tx Enable (R2/14) bit of the register map is also asserted which places the
RFDATA pin into the input state at the completion of the SPI write cycle.
4.10 TX WARM UP
The MC13180 begins a series of internal warm up sequences once the RTXEN pin is asserted. SPI
operations are forbidden during this state.
4.11 TX MODE
Data presented to the RFDATA pin is transmitted to the PA output of the device. SPI operations are
forbidden during this state. The TX mode is ended by de
-
asserting the RTXEN pin or by going into the
RESET state. SPI operations are not permitted until T
TXDIS
μs after the RTXEN pin is de
-
asserted.
4.12 RX CONFIG State
During this state, the contents of the register map are set for any desired receive information, including the
receive channel setting. The Rx Enable (R2/13) bit of the register map is also asserted which places the
RFDATA pin into the output state at the completion of the SPI write cycle.
4.13 RX WARM UP
The MC13180 begins a series of internal warm up sequences once the RTXEN pin is asserted. SPI
operations are forbidden during this state.
4.14 RX MODE
Digitized and oversampled data from the desired receive channel is presented to the RFDATA pin and
framed by the FS signal. Data is aligned to the rising edge of the CLK output. SPI operations are forbidden
during this state. The RX mode is ended by de
-
asserting the RTXEN pin or by going into the RESET state.
SPI operations are not permitted until T
RXDIS
μs after the RTXEN pin is de
-
asserted.