參數(shù)資料
型號(hào)： MC13180
廠(chǎng)商： MOTOROLA INC
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： 2.4 GHz Low Power Wireless Transceiver IC for Bluetooth⑩ Applications
中文描述： SPECIALTY TELECOM CIRCUIT, PQCC48
封裝： PLASTIC, QFN-48
文件頁(yè)數(shù)： 30/58頁(yè)
文件大?。?/td> 992K
代理商： MC13180
30
MC13180 Product Preview
MOTOROLA
Functional Description
4.20 Serial Peripheral Interface (SPI)
Basic functionality of the MC13180 is controlled by configuring the internal address map of the device
(see Figure 4). The address map is completely read/writable and is organized as 32 addresses of 2
-
bytes
(16
-
bits) each. The serial interface to this map is controlled by the CE, SDATA, and SCK pins. In addition,
the entire address map can be placed into a known state by either asserting the RES pin or by writing to
address zero of the device. Logic interface levels are controlled by the VDDINT pin. The interface signal
levels are internally translated to/from VDDINT to VDD.
The non
-
standard SPI uses a bi
-
directional SDATA pin to transfer information to/from the MC13180. Data
is clocked into and out of the device on the rising edge of SCK (SCK is of RZ format). The CE pin enables
the device SPI and transfers the contents of the SPI shift register to the decoded address when de
-
asserted.
The MC13180 device address is defined to be 01 (binary). This scheme allows for up to three additional
SPI devices to be cascaded together without requiring an additional chip enable line.
Figure 13 shows a SPI write operation. SPI transfers begin with the assertion of the CE pin when RES is
de
-
asserted. The first bit clocked into the SPI is the R/W bit which equals a logic zero to indicate a SPI
write operation. The next two bits are the MC13180 device address (i.e., 01). The remaining five bits of the
address field represent the target address to which information will be transferred.
The data field proceeds the address field. Data is clocked into the SPI from MSB to LSB. Once the LSB
has been entered, the CE pin is de
-
asserted and the data field contents are transferred to the MC13180's
target address. A SPI write to address zero resets all register map values to their initial (reset) condition.
Figure 13 also shows a SPI read operation. The first bit clocked into the SPI is now a logic one, indicating
a read operation is desired. Again, the next two bits clocked into the SPI are 01, the MC13180 device
address. The next five bits of the address field will be the target address to be read.
On the falling edge of the SCK, the SDATA line becomes high impedance. This condition remains until
the next rising edge of SCK, where data is driven onto the SDATA pin. Data should be sampled for
reading on the falling edge of SCK.
Once all data has been shifted out of the SPI, the CE pin is de
-
asserted and the SDATA line becomes an
input to the MC13180. Again, reading from address zero will reset the entire register map values to their
initial condition.
Important Note:
All SPI signals (CE, SCK, and SDATA) should remain completely static during an
active receive or transmit cycle to prevent digital feedthrough to the RF portions of the chip. Failure to
follow this condition can cause severe performance degradation.
Figure 13. SPI Register Map
f
max
R / W
RES
CE
RES
CE
SDATA
0
SCK
SDATA
D1
SCK
SPI Write Operation
SPI Read Operation
D14
…
A1
A0
D15
D14
…
D0
A1
A0
D15
A5
A4
A3
A2
1
1
0
D1
D0
0
0
A5
A4
A3
A2
V
DDINT
0 V
V
DDINT
0 V
V
DDINT
0 V
V
DDINT
0 V
V
DDINT
0 V
V
DDINT
0 V
V
DDINT
0 V
V
DDINT
0 V
Hi
-
Z
T
suCE
T
suD
T
HD
T
HCE
T
prop
R / W
Hi
-
Z
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