參數(shù)資料
型號(hào): MC13180
廠商: MOTOROLA INC
元件分類(lèi): 通信及網(wǎng)絡(luò)
英文描述: 2.4 GHz Low Power Wireless Transceiver IC for Bluetooth⑩ Applications
中文描述: SPECIALTY TELECOM CIRCUIT, PQCC48
封裝: PLASTIC, QFN-48
文件頁(yè)數(shù): 31/58頁(yè)
文件大?。?/td> 992K
代理商: MC13180
Functional Description
MOTOROLA
MC13180
Product Preview
31
4.21 Crystal Oscillator
The crystal oscillator provides the reference for the data clock PLL and main PLL. It can be configured as
a Colpitts type (negative resistance) oscillator and utilize an external parallel resonant crystal or may be
driven from an external source. The oscillator circuit has an on
-
chip capacitor trim network that provides
the capability to compensate for crystal and/or load capacitor tolerances. This allows the use of relatively
inexpensive crystals with as much as 50 ppm tolerance. The oscillator also provides three bias current
modes. Xtal Enable (R11/0) enables/disables the bias current and Xtal Boost Enable (R11/4) enables/
disables a high current mode. Refer to the Reference Oscillator Electrical Characteristics for the available
current modes. Table 15 gives examples of parallel trim capacitances that can be programmed to register
map location Xtal Trim (R6/14
-
10). Typical stray capacitance is on the order of 1.0 pF.
To drive the oscillator with an external source, program the Xtal Enable (R11/0) to zero and ac
-
couple the
external signal into the oscillator base with a 15 to 100 pF capacitor. It is also recommended to set Xtal
Trim (R6/14
-
10) to zero to reduce the load on the external source.
Additional characteristic data is shown in Figures 14 through 19.
Table 15.
Examples of Programmable XTAL Trim Capacitances
XTAL Trim (R6/14
-
10) Setting
(MSB to left)
Electronic Parallel Crystal Trim Capacitance
(C
PT
)
00000
0 pF
00100
1.2 pF
10000
4.8 pF
10101
6.3 pF
11111
9.3 pF
Figure 14. Oscillator Open Loop Gain versus
Capacitor Ratio
Figure 15. Oscillator Negative Resistance versus
Electronic Parallel Crystal Trim (C
PT
)
(Crystal Boost Enable R11/4) = 0
O
16
14
12
10
8.0
6.0
4.00
CRYSTAL CAPACITOR RATIO (C5/C8)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
See Figure42, T
A
= 25°C
Open Loop Gain Measurements @ -10 dBm
Crystal Load Capacitance = 13 pF
Electronic Trim (R6/14-10) = 16 (decimal)
O
)
0
T
A
= -20°C
25°C
85°C
-50
-100
-150
-200
-250
-300
-350
0
ELECTRONIC PARALLEL CRYSTAL TRIM (R6/14-10)
4.0
8.0
12
16
20
24
28
32
See Figure42, T
A
= 25°C
Curve Measured with 13 MHz Crystal Reference
Crystal Load Capacitance Ratio = 1.8 (C5/C6)
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