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參數資料
| 型號： | MC13180 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | 2.4 GHz Low Power Wireless Transceiver IC for Bluetooth⑩ Applications |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQCC48 |
| 封裝： | PLASTIC, QFN-48 |
| 文件頁數： | 48/58頁 |
| 文件大?。?/td> | 992K |
| 代理商： | MC13180 |
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48
MC13180 Product Preview
MOTOROLA
Applications Information
5 Applications Information
5.1 General Purpose Output (GPO)
The GPO must be set to a logic one during a transmit cycle and set to a logic zero during a receive cycle
via a SPI write operation, when driving an external antenna switch as shown in Figure 42. When the GPO
is not actively used to drive a peripheral, R2/8 in the address register map is considered a don't care.
5.2 General Purpose Output Invert (GPO Invert)
The MC13180 General Purpose Output (GPO) Invert bit (R3/6) can be used to invert the output value of
GPO located at Pin 9 of the device. The default setting for GPO Invert is zero (i.e., no inversion). When it
is set to one, the GPO output pin assumes the inverted value of GPO in the register map location R2/8. This
is a useful feature when an inverter is not available. It can serve as a complement to GPO Invert.
5.3 External Power Amplifier Enable (EPAEN)
The External Power Amplifier Enable (EPAEN) bit, R6/15, can be used in two applications. It may serve
as a complementary driver to a dual
-
port antenna. This is accomplished when External PA Enable Invert,
R3/10, is set to a logic one. In this configuration, EPAEN assumes the inverted value of GPO, which is the
second driver for the antenna switch.
EPAEN may also assist in Class 1 operation by setting bit R11/6 to a logic high. This setting allows the
MC13180 to drive an external power amplifer. Setting bits R11/6 and R3/10 to zero disables EPAEN.
5.4 External Power Amplifier DAC (EPADAC)
The Bluetooth specification for Class 1 Power implementation requires power control from 4.0 dBm (or
less) to 20 dBm (max) power. The MC13180 external power amplifier digital to analog converter
(EPADAC) output (Pin 10) provides a voltage reference for power control of an external power amplifier
(PA), if desired.
The EPADAC output is enabled when External PA DAC Enable (R11/7) is set to one. Setting R11/7 to
zero pulls the EPADAC output to ground. When enabled, the EPADAC output voltage is controlled by the
PA DAC setting (R3/5
-
0). The minimum EPADAC output voltage is 0 Vdc and the maximum output
voltage is 3.2 Vdc. The 6
-
bit resolution of the PA DAC setting corresponds to approximately 50 mV/bit.
When using a V
CC
RF < 3.2 Vdc, the maximum EPADAC output voltage is reduced to V
CC
RF (i.e., the
full
-
scale output of the PA DAC is referenced to 3.2 V).
To obtain optimum functionality of EPADAC with an external PA, this feature should be utilized with the
External PA Enable. Refer to the Applications Information section for additional usage information. The
output of the EPADAC, when enabled, is gated by the MC13180 sequence manager. During a Sleep, Idle,
or RX cycle, the output is set to zero volts. The programmed value of the output voltage is only achieved
during an active TX cycle as shown in Figure 38.
5.5 PIN Implementation of Antenna Switch
An alternative approach to using an RF switch is to utilize a PIN diode technique as shown in Figure 39.
When both PIN diodes are in the high resistance (i.e., un
-
biased) state, the transmitter is isolated from the
antenna and LNA input. Conversely, when both PIN diodes are in the low resistance (i.e., forward
-
biased)
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