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參數資料
| 型號： | MC34982PNA |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Single Intelligent High-Current Self-Protected Silicon High-Side Switch (2.0 mOhm)(單智能大電流帶自保護功能的硅高端開關（2mOhm）) |
| 中文描述： | 單智能大電流的自我保護硅高邊開關（2.0毫歐）（單智能大電流帶自保護功能的硅高端開關（2mOhm）） |
| 文件頁數： | 15/24頁 |
| 文件大?。?/td> | 771K |
| 代理商： | MC34982PNA |
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33982
15
SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33982 is a self-protected silicon 2.0 m
high-side switch
used to replace electromechanical relays, fuses, and discrete
devices in power management applications. The 33982 is
designed for harsh environments, and it includes self-recovery
features. The device is suitable for loads with high inrush
current, as well as motors and all types of resistive and
inductive loads.
Programming, control, and diagnostics are implemented via
the Serial Peripheral Interface (SPI). A dedicated parallel input
is available for alternate and pulse width modulation (PWM)
control of the output. SPI programmable fault trip thresholds
allow the device to be adjusted for optimal performance in the
application.
The 33982 is packaged in a power-enhanced 12 x 12 PQFN
package with exposed tabs.
FUNCTIONAL DESCRIPTION
SPI Protocol Description
The SPI interface has a full duplex, three-wire synchronous
data transfer with four I/O lines associated with it: Serial Clock
(SCLK), Serial Input (SI), Serial Output (SO), and Chip Select
(
CS
).
The SI/SO terminals of the 33982 follow a first-in first-out
(D7/D0) protocol with both input and output words transferring
the most significant bit (MSB) first. All inputs are compatible
with 5.0 V CMOS logic levels.
The SPI lines perform the following functions:
Serial Clock (SCLK)
The SCLK terminal clocks the internal shift registers of the
33982 device. The serial input terminal (SI) accepts data into
the input shift register on the falling edge of the SCLK signal
while the serial output terminal (SO) shifts data information out
of the SO line driver on the rising edge of the SCLK signal. It is
important that the SCLK terminal be in a logic LOW state
whenever
CS
makes any transition. For this reason, it is
recommended that the SCLK terminal be in a logic [0] state
whenever the device is not accessed (
CS
logic [1] state). SCLK
has an internal pull-down, I
DWN
. When
CS
is logic [1], signals at
the SCLK and SI terminals are ignored and SO is tri-stated
(high impedance). (See
Figure 7
and
Figure 8
on page 16.)
Serial Interface (SI)
This is a serial interface (SI) command data input terminal. SI
instruction is read on the falling edge of SCLK. An 8-bit stream
of serial data is required on the SI terminal, starting with D7 to
D0. The internal registers of the 33982 are configured and
controlled using a 4-bit addressing scheme, as shown in
Table 1
, page 16. Register addressing and configuration are
described in
Table 2
, page 17. The SI input has an internal pull-
down, I
DWN
.
Serial Output (SO)
The SO terminal is a tri-stateable output from the shift
register. The SO terminal remains in a high-impedance state
until the
CS
terminal is put into a logic [0] state. The SO data is
capable of reporting the status of the output, the device
configuration, and the state of the key inputs. The SO terminal
changes states on the rising edge of SCLK and reads out on the
falling edge of SCLK. Fault and input status descriptions are
provided in
Table 8
, page 19.
Chip Select (CS)
The
CS
terminal enables communication with the master
microcontroller (MCU). When this terminal is in a logic [0] state,
the device is capable of transferring information to and
receiving information from the MCU. The 33982 latches in data
from the input shift registers to the addressed registers on the
rising edge of
CS
. The device transfers status information from
the power output to the shift register on the falling edge of
CS
.
The SO output driver is enabled when
CS
is logic [0].
CS
should
transition from a logic [1] to a logic [0] state only when SCLK is
a logic [0].
CS
has an internal pull-up, I
UP
.
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
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