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參數(shù)資料
| 型號： | MC34982PNA |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Single Intelligent High-Current Self-Protected Silicon High-Side Switch (2.0 mOhm)(單智能大電流帶自保護(hù)功能的硅高端開關(guān)（2mOhm）) |
| 中文描述： | 單智能大電流的自我保護(hù)硅高邊開關(guān)（2.0毫歐）（單智能大電流帶自保護(hù)功能的硅高端開關(guān)（2mOhm）） |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 771K |
| 代理商： | MC34982PNA |
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33982
21
During the Fail-Safe mode, the output will be ON or OFF
depending upon the resistor RFS connected to the FSI terminal,
regardless of the state of the various direct inputs and modes
(
Table 12
). In this mode, the SPI register content is retained
except for overcurrent high and low detection levels and timing,
which are reset to their default value (SOCL, SOCH, OCLT).
The watchdog, overvoltage, overtemperature, and overcurrent
circuitry (with default value for this one) are fully operational.
The Fail-Safe mode can be detected by monitoring the
WDTO bit D2 of the WDR register. This bit is logic [1] when the
device is in Fail-Safe mode. The device can be brought out of
the Fail-Safe mode by transitioning the WAKE and
RST
terminals from logic [1] to logic [0] or forcing the FSI terminal to
logic [0].
Table 11
, page 20, summarizes the various methods
for resetting the device from the latched Fail-Safe mode.
If the FSI terminal is tied to GND, the Watchdog fail-safe
operation is disabled.
Loss of V
DD
If the external 5.0 V supply is not within specification, or even
disconnected, all register content is reset. The output can still
be driven by the direct input IN. The 33982 uses the battery
input to power the output MOSFET-related current sense
circuitry and any other internal logic, providing fail-safe device
operation with no V
DD
supplied. In this state, the watchdog,
overvoltage, overtemperature, and overcurrent circuitry are
fully operational with default values.
Fault Mode
The 33982 indicates the following faults as they occur by
driving the
FS
terminal to [0]:
Overtemperature fault
Overvoltage and undervoltage fault
Open load fault
Overcurrent fault (high and low)
The
FS
terminal will automatically return to [1] when the fault
condition is removed, except for overcurrent and in some cases
undervoltage.
Fault information is retained in the fault register and is
available (and reset) via the SO terminal during the first valid
SPI communication (refer to
Table 9
, page 19).
Overtemperature Fault (Non-Latching)
The 33982 incorporates overtemperature detection and
shutdown circuitry in the output structure. Overtemperature
detection is enabled when the output is in the ON state.
For the output, an overtemperature fault (OTF) condition
results in the faulted output turning OFF until the temperature
falls below the T
SD(HYS)
. This cycle will continue indefinitely
until action is taken by the MCU to shut OFF the output, or until
the offending load is removed.
When experiencing this fault, the OTF fault bit will be set in
the status register and cleared after either a valid SPI read or a
power reset of the device.
Overvoltage Fault (Non-Latching)
The 33982 shuts down the output during an overvoltage fault
(OVF) condition on the V
PWR
terminal. The output remains in
the OFF state until the overvoltage condition is removed. When
experiencing this fault, the OVF fault bit is set in bit OD1 and
cleared after either a valid SPI read or a power reset of the
device.
The overvoltage protection and diagnostic can be disabled
through SPI (bit OV_dis).
Undervoltage Shutdown (Latching or Non-Latching)
The output latches OFF at some battery voltage between
5.0 V and 6.0 V. As long as the V
DD
level stays within the
normal specified range, the internal logic states within the
device will be sustained. This ensures that when the battery
level then returns above 6.0 V, the device can be returned to
the state that it was in prior to the low V
PWR
excursion. Once the
output latches OFF, the outputs must be turned OFF and ON
again to re-enable them. In the case IN=0, this fault is non-
latched.
The undervoltage protection and diagnostic can be disabled
through SPI (bit UV_dis).
Open Load Fault (Non-Latching)
The 33982 incorporates open load detection circuitry on the
output. Output open load fault (OLF) is detected and reported
as a fault condition when the output is disabled (OFF). The
open load fault is detected and latched into the status register
after the internal gate voltage is pulled low enough to turn OFF
the output. The OLF fault bit is set in the status register. If the
open load fault is removed, the status register will be cleared
after reading the register.
The open load protection can be disabled through SPI (bit
OL_dis).
Table 12. Output State During
Fail-Safe Mode
RFS (k
)
High-Side State
0
Fail-Safe Mode Disabled
10
HS OFF
30
HS ON
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
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