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參數(shù)資料
| 型號： | MC34982PNA |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Single Intelligent High-Current Self-Protected Silicon High-Side Switch (2.0 mOhm)(單智能大電流帶自保護功能的硅高端開關(guān)（2mOhm）) |
| 中文描述： | 單智能大電流的自我保護硅高邊開關(guān)（2.0毫歐）（單智能大電流帶自保護功能的硅高端開關(guān)（2mOhm）） |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 771K |
| 代理商： | MC34982PNA |
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33982
19
logic [0] during SPI communication and/or for the period of time
since the last valid SPI communication, with the following
exceptions:
The previous SPI communication was determined to be
invalid. In this case, the status will be reported as though
the invalid SPI communication never occurred.
Battery transients below 6.0 V resulting in an under-
voltage shutdown of the outputs may result in incorrect
data loaded into the status register. The SO data
transmitted to the MCU during the first SPI communication
following an undervoltage V
PWR
condition should be
ignored.
The
RST
terminal transition from a logic [0] to [1] while the
WAKE terminal is at logic [0] may result in incorrect data
loaded into the status register. The SO data transmitted to
the MCU during the first SPI communication following this
condition should be ignored.
Serial Output Bit Assignment
The eight bits of serial output data depend on the previous
serial input message, as explained in the following paragraphs.
Table 8
summarizes the SO register content.
Bit OD7 reflects the state of the watchdog bit (D7) addressed
during the prior communication. The contents of bits OD[6:0]
depend upon the bits D[2:0] from the most recent STATR
command SOA[2:0].
Previous Address SOA[2:0]=000
If the previous three MSBs are 000, bits OD6–OD0 reflect
the current state of the fault register (FLTR) (
Table 9
).
Previous Address SOA[2:0]=001
The data in bits OD1 and OD0 contain CSNS
EN
and IN_SPI
programmed bits, respectively.
Previous Address SOA[2:0]=010
The data in bit OD3 contain the programmed overcurrent
high detection level (refer to
Table 4
, page 17), and the data in
bits OD2, OD1, and OD0 contain the programmed overcurrent
low detection levels (refer to
Table 3
, page 17).
Previous Address SOA[2:0]=011
The data returned in bits OD1 and OD0 are current values for
the overcurrent fault blanking time, illustrated in
Table 5
,
page 17. Bit OD2 reports when the overcurrent detection
timeout feature is active. OD3 reports whether the open load
circuitry is active.
Table 8. Serial Output Bit Map Description
Previous STATR
D7, D2, D1, D0
Serial Output Returned Data
SOA3
SOA2
SOA1
SOA0
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
x
0
0
0
WDin
OTF
OCHF
OCLF
OLF
UVF
OVF
FAULT
x
0
0
1
WDin
0
0
1
0
0
CSNS
EN
IN_SPI
x
0
1
0
WDin
0
1
0
SOCH
SOCL2
SOCL1
SOCL0
x
0
1
1
WDin
0
1
1
OL dis
CD dis
OCLT1
OCLT0
x
1
0
0
WDin
1
0
0
Fast SR
CSNS high
IN dis
A/O
0
1
0
1
0
1
0
1
FSM_HS
OSD2
OSD1
OSD0
1
1
0
1
1
1
0
1
0
WDTO
WD1
WD0
0
1
1
0
0
1
1
0
0
IN Terminal
FSI Terminal
WAKE Terminal
1
1
1
0
1
1
1
0
0
0
UV_dis
OV_dis
x
1
1
1
WDin
–
–
–
–
–
–
–
x = Don’t care.
Table 9. Fault Register
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
x
OTF
OCHF
OCLF
OLF
UVF
OVF
FAULT
OD7 (x) = Don’t care.
OD6 (OTF) = Overtemperature Flag.
OD5 (OCHF) = Overcurrent High Flag. (This fault is latched.)
OD4 (OCLF) = Overcurrent Low Flag. (This fault is latched.)
OD3 (OLF) = Open Load Flag.
OD2 (UVF) = Undervoltage Flag. (This fault is latched or not latched.)
OD1 (OVF) = Overvoltage Flag.
OD0 (FAULT) = This flag reports a fault and is reset by a read operation.
Note
The
FS
terminal reports a fault and is reset by a new Switch-ON
command (via SPI or direct input IN).
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
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