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參數(shù)資料
| 型號： | MC34982PNA |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Single Intelligent High-Current Self-Protected Silicon High-Side Switch (2.0 mOhm)(單智能大電流帶自保護功能的硅高端開關（2mOhm）) |
| 中文描述： | 單智能大電流的自我保護硅高邊開關（2.0毫歐）（單智能大電流帶自保護功能的硅高端開關（2mOhm）） |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 771K |
| 代理商： | MC34982PNA |
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33982
17
Device Register Addressing
The following section describes the possible register
addresses and their impact on device operation.
Address x000—Status Register (STATR)
The STATR register is used to read the device status and the
various configuration register contents without disrupting the
device operation or the register contents. The register bits D2,
D1, and D0 determine the content of the first eight bits of SO
data. In addition to the device status, this feature provides the
ability to read the content of the OCR, SOCHLR, CDTOLR,
DICR, OSDR, WDR, NAR, and UOVR registers. (Refer to the
section entitled
Serial Output Communication (Device Status
Return Data)
beginning on page 18.)
Address x001—Output Control Register (OCR)
The OCR register allows the MCU to control the output
through the SPI. Incoming message bit D0 (IN_SPI) reflects the
desired states of the high-side output: a logic [1] enables the
output switch and a logic [0] turns it OFF. A logic [1] on
message bit D1 enables the Current Sense (CSNS) terminal.
Bits D2 and D3 must be logic [0]. Bit D7 is used to feed the
watchdog if enabled.
Address x010—Select Overcurrent High and Low Register
(SOCHLR)
The SOCHLR register allows the MCU to configure the
output overcurrent low and high detection levels, respectively.
In addition to protecting the device, this slow blow fuse
emulation feature can be used to optimize the load
requirements to match system characteristics. Bits D2–D0 are
used to set the overcurrent low detection level to one of eight
possible levels are shown in
Table 3
. Bit D3 is used to set the
overcurrent high detection level to one of two levels as outlined
in
Table 4
.
Address x011—Current Detection Time and Open Load
Register (CDTOLR)
The CDTOLR register is used by the MCU to determine the
amount of time the device will allow an overcurrent low
condition before output latches OFF occurs. Bits D1 and D0
allow the MCU to select one of four fault blanking times defined
in
Table 5
. Note that these timeouts apply only to the
overcurrent low detection levels. If the selected overcurrent
high level is reached, the device will latch off within 20
μ
s
.
A logic [1] on bit D2 disables the overcurrent low (CD dis)
detection timeout feature. A logic [1] on bit D3 disables the open
load (OL) detection feature.
Address x100—Direct Input Control Register (DICR)
The DICR register is used by the MCU to enable, disable, or
configure the direct IN terminal control of the output. A logic [0]
on bit D1 will enable the output for direct control by the IN
terminal. A logic [1] on bit D1 will disable the output from direct
control. While addressing this register, if the input was enabled
for direct control, a logic [1] for the D0 bit will result in a Boolean
AND of the IN terminal with its corresponding D0 message bit
when addressing the OCR register. Similarly, a logic [0] on the
D0 terminal will result in a Boolean OR of the IN terminal with
Table 2. Serial Input Address and Configuration Bit Map
SI
Register
Serial Input Data
D7 D6 D5 D4
D3
D2
D1
D0
STATR
x
0
0
0
0
SOA2
SOA1
SOA0
OCR
x
0
0
1
0
0
CSNS
EN
IN_SPI
SOCHLR
x
0
1
0
SOCH
SOCL2
SOCL1
SOCL0
CDTOLR
x
0
1
1
OL dis
CD dis
OCLT1
OCLT0
DICR
x
1
0
0
FAST
SR
CSNS
high
IN dis
A/O
OSDR
0
1
0
1
0
OSD2
OSD1
OSD0
WDR
1
1
0
1
0
0
WD1
WD0
NAR
0
1
1
0
0
0
0
0
UOVR
1
1
1
0
0
0
UV_dis
OV_dis
TEST
x
1
1
1
Motorola Internal Use (Test)
x = Don’t care.
Table 3. Overcurrent Low Detection Levels
SOCL2
(D2)
SOCL1
(D1)
SOCL0
(D0)
Overcurrent Low Detection
(Amperes)
0
0
0
50
0
0
1
45
0
1
0
40
0
1
1
35
1
0
0
30
1
0
1
25
1
1
0
20
1
1
1
15
Table 4. Overcurrent High Detection Levels
SOCH (D3)
Overcurrent High Detection
(Amperes)
0
150
1
100
Table 5. Overcurrent Low Detection
Blanking Time
OCLT[1:0]
Timing
00
155 ms
01
10 ms
10
1.2 ms
11
150
μ
s
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
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