Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)
MC9S12XE-Family Reference Manual Rev. 1.21
Freescale Semiconductor
509
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13.3.2.3
ATD Control Register 2 (ATDCTL2)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
Module Base + 0x0002
76543210
R0
AFFC
ICLKSTP
ETRIGLE
ETRIGP
ETRIGE
ASCIE
ACMPIE
W
Reset
0
00000
= Unimplemented or Reserved
Figure 13-5. ATD Control Register 2 (ATDCTL2)
Table 13-7. ATDCTL2 Field Descriptions
Field
Description
6
AFFC
ATD Fast Flag Clear All
0 ATD ag clearing done by write 1 to respective CCF[n] ag.
1 Changes all ATD conversion complete ags to a fast clear sequence.
For compare disabled (CMPE[n]=0) a read access to the result register will cause the associated CCF[n] ag
to clear automatically.
For compare enabled (CMPE[n]=1) a write access to the result register will cause the associated CCF[n] ag
to clear automatically.
5
ICLKSTP
Internal Clock in Stop Mode Bit — This bit enables A/D conversions in stop mode. When going into stop mode
and ICLKSTP=1 the ATD conversion clock is automatically switched to the internally generated clock ICLK.
Current conversion sequence will seamless continue. Conversion speed will change from prescaled bus
frequency to the ICLK frequency (see ATD Electrical Characteristics in device description). The prescaler bits
PRS4-0 in ATDCTL4 have no effect on the ICLK frequency. For conversions during stop mode the automatic
compare interrupt or the sequence complete interrupt can be used to inform software handler about changing
A/D values. External trigger will not work while converting in stop mode. For conversions during transition from
Run to Stop Mode or vice versa the result is not written to the results register, no CCF ag is set and no compare
is done. When converting in Stop Mode (ICLKSTP=1) an ATD Stop Recovery time tATDSTPRCV is required to
switch back to bus clock based ATDCLK when leaving Stop Mode. Do not access ATD registers during this time.
0 If A/D conversion sequence is ongoing when going into stop mode, the actual conversion sequence will be
aborted and automatically restarted when exiting stop mode.
1 A/D continues to convert in stop mode using internally generated clock (ICLK)
4
ETRIGLE
External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See
3
ETRIGP
External Trigger Polarity — This bit controls the polarity of the external trigger signal. See
Table 13-8 for details.
2
ETRIGE
External Trigger Mode Enable — This bit enables the external trigger on one of the AD channels or one of the
ETRIG3-0 inputs as described in
Table 13-6. If external trigger source is one of the AD channels, the digital input
buffer of this channel is enabled. The external trigger allows to synchronize the start of conversion with external
events. External trigger will not work while converting in stop mode.
0 Disable external trigger
1 Enable external trigger