參數(shù)資料
型號(hào): MC68CK338
廠商: Motorola, Inc.
元件分類: 32位微控制器
英文描述: Highly Integrated, Low-Power, 32-Bit Microcontroller
中文描述: 高度集成,低功耗,32位微控制器
文件頁數(shù): 36/133頁
文件大?。?/td> 798K
代理商: MC68CK338
MOTOROLA
36
MC68CK338
MC68CK338TS/D
CSORBT, the option register for CSBOOT, contains special reset values that support bootstrap opera-
tion from peripheral memory devices.
The following bit descriptions apply to both CSORBT and CSOR[0:10] option registers.
MODE — Asynchronous/Synchronous Mode
0 = Asynchronous mode (chip-select assertion determined by bus control signals)
1 = Synchronous mode (chip-select assertion synchronized with ECLK signal)
In asynchronous mode, the chip-select is asserted synchronized with AS or DS.
DSACK[3:0] is not used in synchronous mode because a bus cycle is only performed as a synchronous
operation. When a match condition occurs on a chip-select programmed for synchronous operation, the
chip-select signals the EBI that an ECLK cycle is pending.
BYTE[1:0] — Upper/Lower Byte Option
This field is used only when the chip-select 16-bit port option is selected in the pin assignment register.
Table 24
lists upper/lower byte options.
R/W[1:0] — Read/Write
This field causes a chip-select to be asserted only for reads, only for writes, or for both reads and writes.
Refer to
Table 25
for options available.
STRB — Address Strobe/Data Strobe
0 = Address strobe
1 = Data strobe
This bit controls the timing for assertion of a chip-select in asynchronous mode. Selecting address
strobe causes chip-select to be asserted synchronized with address strobe. Selecting data strobe caus-
es chip-select to be asserted synchronized with data strobe.
DSACK[3:0] — Data and Size Acknowledge
This field specifies the source of DSACK[3:0] in asynchronous mode. It also allows the user to adjust
bus timing with internal DSACK[3:0] generation by controlling the number of wait states that are inserted
to optimize bus speed in a particular application.
Table 26
shows the DSACK[3:0] encoding. The fast
termination encoding (%1110) is used for two-cycle access to external memory.
Table 24 Upper/Lower Byte Options
BYTE[1:0]
00
01
10
11
Description
Disable
Lower Byte
Upper Byte
Both Bytes
Table 25 R/W Encodings
R/W[1:0]
00
01
10
11
Description
Reserved
Read Only
Write Only
Read/Write
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