參數(shù)資料
型號: MC68CK338
廠商: Motorola, Inc.
元件分類: 32位微控制器
英文描述: Highly Integrated, Low-Power, 32-Bit Microcontroller
中文描述: 高度集成,低功耗,32位微控制器
文件頁數(shù): 92/133頁
文件大小: 798K
代理商: MC68CK338
MOTOROLA
92
MC68CK338
MC68CK338TS/D
IN2 — Clock Input Pin Status
This read-only status bit reflects the logic state of the clock input pin. Writing to this bit has no effect,
nor does reset.
NOTE
The clock input of MCSM2 is internally connected to I/O pin CTD27 for DASM27
and will read the state of that pin. The clock inputs of MCSM30 and MCSM31 are
internally connected to I/O pin CTD5 for DASM5 and will read the state of that pin.
IN1 — Modulus Load Input Pin Status
This read-only status bit reflects the logic state of the modulus load input pin. Writing to this bit has no
effect, nor does reset.
NOTE
The load input of MCSM2 is internally connected to I/O pin CTD29 for DASM29 and
will read the state of that pin. The load input of MCSM30 is internally connected to
I/O pin CTD4 for DASM4 and will read the state of that pin. The load input of
MCSM31 is available externally on the CTM31L pin.
EDGEN, EDGEP — Modulus Load Edge Sensitivity Bits
These read/write control bits select the sensitivity of the edge detection circuitry on the modulus load
pin CTML. Refer to
Table 53
.
CLK[2:0] — Counter Clock Select
These read/write control bits select one of six internal clock signals (PCLK[1:6]) or one of two external
conditions on the external clock input pin (rising edge or falling edge). The maximum frequency of the
external clock signals is f
sys
/4. Refer to
Table 54
.
Table 53 Modulus Load Edge Sensitivity
EDGEN
0
0
1
1
EDGEP
0
1
0
1
IN1 Edge Detector Sensitivity
None
Positive edge only
Negative edge only
Positive and negative edge
Table 54 Counter Clock Select
CLK2
CLK1
CLK0
Free-Running Counter Clock Source
PCLK1 (f
sys
÷
2 or f
sys
÷
3)
PCLK2 (f
sys
÷
4 or f
sys
÷
6)
PCLK3 (f
sys
÷
8 or f
sys
÷
12)
PCLK4 (f
sys
÷
16 or f
sys
÷
24)
PCLK5 (f
sys
÷ 3
2 or f
sys
÷
48)
PCLK6 (f
sys
÷
64 or f
sys
÷
768)
External clock input, falling edge
External clock input, rising edge
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
1
1
0
1
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