參數(shù)資料
型號： MC68CK338
廠商： Motorola, Inc.
元件分類： 32位微控制器
英文描述： Highly Integrated, Low-Power, 32-Bit Microcontroller
中文描述： 高度集成，低功耗，32位微控制器
文件頁數(shù)： 65/133頁
文件大?。?/td> 798K
代理商： MC68CK338
MC68CK338
MC68CK338TS/D
MOTOROLA
65
5.5.1 QSPI Pins
Seven pins are associated with the QSPI. When not needed for a QSPI function, they can be configured
as general-purpose I/O pins. The PCS0/SS pin can function as a peripheral chip select output, slave
select input, or general-purpose I/O. Refer to
Table 39
for QSPI input and output pins and their func-
tions.
5.5.2 QSPI Registers
The programmer's model for the QSPI submodule consists of the QSM global and pin control registers,
four QSPI control registers, one status register, and the 80-byte QSPI RAM.
The CPU can read and write to registers and RAM. The four control registers must be initialized before
the QSPI is enabled to ensure defined operation. SPCR1 should be written last because it contains
QSPI enable bit SPE. Asserting this bit starts the QSPI. The QSPI control registers are reset to a de-
fined state and can then be changed by the CPU. Reset values are shown below each register.
Table 40
shows a memory map of the QSPI.
Writing a different value into any control register except SPCR2 while the QSPI is enabled disrupts op-
eration. SPCR2 is buffered to prevent disruption of the current serial transfer. After completion of the
current serial transfer, the new SPCR2 values become effective.
Writing the same value into any control register except SPCR2 while the QSPI is enabled has no effect
on QSPI operation. Rewriting NEWQP[3:0] in SPCR2 causes execution to restart at the designated
location.
Table 39 QSPI Pins
Pin Name(s)
Mnemonic(s)
Mode
Master
Slave
Master
Slave
Master
Slave
Master
Master
Master
Slave
Function
Master In Slave Out
MISO
Serial data input to QSPI
Serial data output from QSPI
Serial data output from QSPI
Serial data input to QSPI
Clock output from QSPI
Clock input to QSPI
Select peripherals
Selects peripheral
Causes mode fault
Initiates serial transfer
Master Out Slave In
MOSI
Serial Clock
SCK
Peripheral Chip Selects
PCS[3:1]
Peripheral Chip Select
Slave Select
PCS0
SS
Table 40 QSPI Memory Map
Address
$YFFC18
$YFFC1A
$YFFC1C
$YFFC1E
$YFFC1F
$YFFD00
$YFFD20
$YFFD40
Name
SPCR0
SPCR1
SPCR2
SPCR3
SPSR
RR[0:F]
TR[0:F]
CR[0:F]
Usage
QSPI control register 0
QSPI control register 1
QSPI control register 2
QSPI control register 3
QSPI status register
QSPI receive data (16 words)
QSPI transmit data (16 words)
QSPI command control (8 words)
相關(guān)PDF資料
PDF描述
MC68EC060 32-Bit Microprocessors.(32位微處理器)
MC68EN360RC25V QUad Integrated Communications Controller Users Manual
MC68EN360CFE25 QUad Integrated Communications Controller Users Manual
MC68EN360FE25 AC 4C 4#12 PIN PLUG 023
MC68EN360FE25V QUad Integrated Communications Controller Users Manual
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