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參數(shù)資料
| 型號： | MC68CK338 |
| 廠商： | Motorola, Inc. |
| 元件分類： | 32位微控制器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 高度集成，低功耗，32位微控制器 |
| 文件頁數(shù)： | 98/133頁 |
| 文件大?。?/td> | 798K |
| 代理商： | MC68CK338 |
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MOTOROLA
98
MC68CK338
MC68CK338TS/D
The DASM is composed of two timing channels (A and B), an output flip-flop, an input edge detector,
some control logic and an interrupt interface. All control and status bits are contained in the DASMSIC
register.
Channel A consists of one 16-bit data register and one 16-bit comparator. To the user, channel B also
appears to consist of one 16-bit data register and one 16-bit comparator, though internally, channel B
has two data registers (B1 and B2). The operating mode determines which register is accessed by the
software. Refer to
Table 59
.
Register contents are always transferred automatically at the correct time so that the minimum pulse
(measurement or generation) is just one time base bus count. The A and B data registers are always
read/write registers, accessible via the CTM6 submodule bus.
Eleven DASMs are contained in the CTM6.
Figure 23
shows a block diagram of the DASM.
Table 58 DASM Modes of Operation
Mode
DIS
IPWM
IPM
IC
Description of Mode
Disabled — I/O pin is placed in a high impedance state
Input pulse width measurement — Capture on leading and the trailing edges of an input pulse
Input period measurement — Capture on two consecutive rising or falling edges of an input pulse
Input capture — Capture on user-specified edge
Output compare, flag set on channel B match — Generate leading and trailing edges of an output
pulse and set flag on second edge
Output compare, flag set on channels A and B match — Generate leading and trailing edges of an
output pulse and set flag on both edges
Output pulse width modulation — Generate continuous PWM output with 7, 9, 11, 12, 13, 14, 15, or
16 bits of resolution
OCB
OCAB
OPWM
Table 59 Channel B Data Register Access
Mode
Data Register
IPWM, IPM, IC
Registers A and B2 are used to hold the captured values. In these modes,
the B1 register is used as a temporary latch for channel B.
Registers A and B2 are used to define the output pulse. Register B1 is not
used in these modes.
Registers A and B1 are used as primary registers and hidden register B2 is
used as a double buffer for channel B.
OCA, OCAB
OPWM
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68CM16Z1 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series |
| MC68CM16Z1CFC16 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series |
| MC68CM16Z1CPV16 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series |
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