參數(shù)資料
型號(hào): MC68HC05C5P
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝: DIP-40
文件頁(yè)數(shù): 15/58頁(yè)
文件大小: 166K
代理商: MC68HC05C5P
Page 16
MOTOROLA
Section 4: CPU Core
MC68HC05C5 Specification Rev. 1.2
4.1.2
INDEX REGISTER (X)
The index register is an 8-bit register used for the indexed addressing value to create an
effective address. The index register may also be used as a temporary storage area.
4.1.3
PROGRAM COUNTER (PC)
The program counter is a 13-bit register that contains the address of the next byte to be
fetched.
4.1.4
STACK POINTER (SP)
The stack pointer contains the address of the next free location on the stack. During an
MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location
$00FF. The stack pointer is then decremented as data is pushed onto the stack and
incremented as data is pulled from the stack.
When accessing memory, the seven most significant bits are permanently set to 0000011.
These 7 bits are appended to the six least significant register bits to produce and address
within the range of $00FF to $00C0.
Subroutines and interrupts may use up to 64
(decimal) locations. If 64 locations are exceeded, the stack pointer wraps around and
loses the previously stored information. A subroutine call occupies two locations on the
stack; an interrupt uses five locations.
4.1.5
CONDITION CODE REGISTER (CCR)
The CCR is a 5-bit register in which 4 bits are used to indicate the results of the instruction
just executed, and the fifth bit indicates whether interrupts are masked. These bits can
be individually tested by a program, and specific actions can be taken as a result of their
state. Each bit is explained in the following paragraphs.
4.1.5.1
Half Carry (H)
This bit is set during ADD and ADC operations to indicate that a carry occurred between
bits 3 and 4.
4.1.5.2
Interrupt (I)
When this bit is set, the timer and external interrupt is masked (disabled). If an interrupt
occurs while this bit is set, the interrupt is latched and processed as soon as the interrupt
bit is cleared.
4.1.5.3
Negative (N)
When set, this bit indicates that the result of the last arithmetic, logical, or data
manipulation was negative.
4.1.5.4
Zero (Z)
When set, this bit indicates that the result of the last arithmetic, logical, or data
manipulation was zero.
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