參數(shù)資料
型號: MC68HC05C5P
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝: DIP-40
文件頁數(shù): 26/58頁
文件大小: 166K
代理商: MC68HC05C5P
Page 26
MOTOROLA
Section 4: CPU Core
MC68HC05C5 Specification Rev. 1.2
NOTE:
The internal interrupt latch is cleared in the first part of the interrupt
service routine; therefore, one external interrupt pulse could be latched
and serviced as soon as the I bit is cleared.
4.5.4
TIMER INTERRUPT
There are three different timer interrupt flags that cause a timer interrupt whenever they
are set and enabled. The interrupt flags are in the Timer Status Register (TSR), and the
enable bits are in the Timer Control Register (TCR). Any of these interrupts will vector to
the same interrupt service routine, located at the address specified by the contents of
memory locations $1FF8 and $1FF9.
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