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參數(shù)資料
| 型號： | MC68HC05C5P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 42/58頁 |
| 文件大?。?/td> | 166K |
| 代理商： | MC68HC05C5P |
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Page 41
Section 7: Simple Input/Output Port
MOTOROLA
MC68HC05C5 Specification Rev. 1.2
7.2.1.1
SPE - SERIAL PERIPHERAL ENABLE
When set, this bit enables the Serial I/O Port and initializes the Port B DDR such that PB5
(SDO) is output, PB6 (SDI) is input and PB7 (SCK) is input (slave mode only). The Port
B DDR can be subsequently altered as the application requires and the Port B data
register (except for PB5) can be manipulated as usual. However, these actions could
affect the transmitted or received data. When SPE is cleared, Port B reverts to standard
parallel I/O without affecting the Port B data register or DDR. SPE is readable and
writable any time but clearing SPE while a transmission is in progress will abort the
transmission, reset the bit counter, and return Port B to its normal I/O function. Reset
clears this bit.
7.2.1.2
MSTR - MASTER MODE
When set, this bit configures the SIOP for master mode. This means that the transmission
is initiated by a write to the data register and the SCK pin becomes an output providing a
synchronous data clock at a fixed rate of E (bus clock) divided by 4. While the device is
in master mode, the SDO and SDI pins do not change function. These pins behave
exactly as they would in slave mode. Reset clears this bit and configures the SIOP for
slave operation. MSTR may be set at any time regardless of the state of SPE. Clearing
MSTR will abort any transmission in progress.
7.2.1.3
CPOL - CLOCK POLARITY
The Clock Polarity bit controls the SCK polarity between transmissions. When this bit is
cleared, SCK will be low between transmissions. When this bit is set, SCK will be high
between transmissions. In both cases, the data is latched on the rising edge of SCK for
serial input and is valid on the rising edge of SCK for serial output. Reset sets this bit.
When using the Clock Polarity low mode (CPOL=0), the proper mode should be entered
before enabling the serial system. The CPOL bit should be cleared first. Then the SPE
bit should be set during a second write to the SCR. The following example shows a proper
sequence.
* For Master Mode CPOL=0
LDA#$00
STASCRclear CPOL
LDA#$50
STASCRset Mstr, set SPE
* For Slave Mode CPOL=0
LDA#$00
STASCRclear CPOL
LDA#$40
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