參數(shù)資料
型號： MC68HC05C5P
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝： DIP-40
文件頁數(shù)： 37/58頁
文件大?。?/td> 166K
代理商： MC68HC05C5P
Page 36
MOTOROLA
Section 6: Timer
MC68HC05C5 Specification Rev. 1.2
ICIE - Input Capture Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
OCIE - Output Compare Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
TOIE - Timer Overflow Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
COE - TCMP Pin Enable
1 = TCMP pin enabled
0 = TCMP pin disabled (pin 35 is PD6)
IEDG - Input Edge
Value of input edge determines which level transition on TCAP pin will trigger free-running
counter transfer to the input capture register
1 = Positive edge
0 = Negative edge
Reset does not affect the IEDG bit (U=unaffected).
OLVL - Output Level
Value of output level is clocked into output level register by the next successful output
compare and will appear on the TCMP pin
1 = High output
0 = Low output
Bits 3 and 4 - Not used
Always read zero
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