參數(shù)資料
型號(hào)： MC68HC05C5P
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝： DIP-40
文件頁(yè)數(shù)： 45/58頁(yè)
文件大?。?/td> 166K
代理商： MC68HC05C5P
Page vii
MOTOROLA
MC68HC05C5 Specification Rev. 1.2
LIST OF FIGURES
Figure 1-1:
Self-Check Mode Schematic for the MC68HC05C5 .................................2
Figure 2-1:
Single-Chip Mode Pinout of the MC68HC05C5........................................6
Figure 2-2:
Self-Check Mode Schematic for the MC68HC05C5 .................................7
Figure 3-1:
The 8K Memory Map of the MC68HC05C5 ..............................................9
Figure 3-2:
I/O Registers for the MC68HC05C5 .......................................................10
Figure 3-3:
Programming Register ............................................................................11
Figure 4-1:
Programming Model ...............................................................................15
Figure 4-2:
Stacking Order ........................................................................................15
Figure 4-3:
Power-On Reset and RESET .................................................................23
Figure 4-4:
Interrupt Flowchart ..................................................................................27
Figure 4-5:
Stop Recovery Timing Diagram ..............................................................28
Figure 4-6:
STOP/WAIT Flowcharts..........................................................................29
Figure 5-1:
Port I/O Circuitry .....................................................................................32
Figure 6-1:
Timer Block Diagram ..............................................................................33
Figure 6-2:
Timer Control Register............................................................................35
Figure 6-3:
Timer Status Register .............................................................................37
Figure 7-1:
SIOP Block Diagram ...............................................................................39
Figure 7-2:
Serial I/O Port Timing (CPOL=1) ............................................................40
Figure 7-3:
Serial I/O Port Timing (CPOL=0) ............................................................40
Figure 7-4:
SIOP Control Register ............................................................................40
Figure 7-5:
SIOP Status Register..............................................................................42
Figure 7-6:
SIOP Data Register ................................................................................42
Figure 9-1:
Stop Recovery Timing Diagram ..............................................................48
Figure 9-2:
LVPI Timing Diagram..............................................................................48
Figure 9-3:
SIOP Timing Diagram .............................................................................49
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