參數(shù)資料
型號(hào)： MC68HC05C5P
廠商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝： DIP-40
文件頁(yè)數(shù)： 38/58頁(yè)
文件大小： 166K
代理商： MC68HC05C5P
Page 37
Section 6: Timer
MOTOROLA
MC68HC05C5 Specification Rev. 1.2
6.6
TIMER STATUS REGISTER (TSR) $13
The TSR is a read-only register containing three status flag bits.
ICF - Input Capture Flag
1 = Flag set when selected polarity edge is sensed by input capture edge detector
0 = Flag cleared when TSR and input capture low register ($15) are accessed
OCF - Output Compare Flag
1 = Flag set when output compare register contents match the free-running counter
contents
0 = Flag cleared when TSR and output compare low register ($17) are accessed
TOF - Timer Overflow Flag
1 = Flag set when free-running counter transition from $FFFF to $0000 occurs
0 = Flag cleared when TSR and counter low register ($19) are accessed
Bits 0-4 - Not used
Always read zero
Accessing the timer status register satisfies the first condition required to clear status bits.
The remaining step is to access the register corresponding to the status bit.
A problem can occur when using the timer overflow function and reading the free-running
counter at random times to measure an elapsed time. Without incorporating the proper
precautions into software, the timer overflow flag could unintentionally be cleared if:
1) The timer status register is read or written when TOF is set, and
2) The LSB of the free-running counter is read but not for the purpose of servicing the flag.
The counter alternate register at address $1A and $1B contains the same value as the
free-running counter (at address $18 and $19); therefore, this alternate register can be
read at any time without affecting the timer overflow flag in the timer status register.
ICF
TOF
00000
OCF
$13
U
00000
U
RESET:
Figure 6-3: Timer Status Register
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